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公开(公告)号:EP0532672A4
公开(公告)日:1993-12-22
申请号:EP91912249
申请日:1991-05-29
IPC分类号: H04N5/46 , G06F3/00 , G06T3/40 , G09G5/00 , G09G5/14 , G09G5/377 , G09G5/391 , H04N3/223 , H04N3/227 , H04N3/27 , H04N5/073 , H04N5/14 , H04N5/262 , H04N5/265 , H04N5/44 , H04N5/45 , H04N7/00 , H04N7/01 , H04N7/015 , H04N7/26 , H04N9/64 , H04N11/06 , H04N11/20 , H04N11/24 , H04N7/18
CPC分类号: H04N9/641 , G06T3/0012 , G06T3/4007 , H04N3/223 , H04N3/227 , H04N3/27 , H04N5/2624 , H04N5/45 , H04N7/007 , H04N7/01 , H04N7/0105 , H04N7/0122 , H04N7/015 , H04N9/64 , H04N19/90
摘要: A video display system comprises analog to digital converters (342, 346) for quantizing first and second video signals, representing first and second pictures respectively, at higher and lower levels of quantization resolution relative to one another. The analog to digital converters (342, 346) can operate at different sampling rates. The picture represented in the lower sampling rate signal can have the appearance of being subsampled, relative to the other picture. A video display is synchronized with the first video signal. The second video signal is synchronized with the first video signal. A signal processing circuit modifies the first and second video signals to represent the first and second pictures respectively in sizes smaller than the video display. A multiplexing circuit (300) combines the processed video signals for side-by-side display of said pictures. A quantization resolution enhancing circuit improves the perceived quality of the video signal having the lower level of quantization resolution.
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公开(公告)号:EP0533738A4
公开(公告)日:1993-12-01
申请号:EP91910761
申请日:1991-05-29
IPC分类号: H04N5/46 , G06F3/00 , G06T3/40 , G09G5/00 , G09G5/14 , G09G5/377 , G09G5/391 , H04N3/223 , H04N3/227 , H04N3/27 , H04N5/073 , H04N5/14 , H04N5/262 , H04N5/265 , H04N5/44 , H04N5/45 , H04N7/00 , H04N7/01 , H04N7/015 , H04N7/26 , H04N9/64 , H04N11/06 , H04N11/20 , H04N11/24
CPC分类号: H04N9/641 , G06T3/0012 , G06T3/4007 , H04N3/223 , H04N3/227 , H04N3/27 , H04N5/2624 , H04N5/45 , H04N7/007 , H04N7/01 , H04N7/0105 , H04N7/0122 , H04N7/015 , H04N9/64 , H04N19/90
摘要: A wide screen television apparatus comprises a video display (244) having a first format display ratio of width to height, for example approximately 16x9. A first video signal defines a first picture. A second video signal defines a second picture in a second format display ratio of width to height smaller than the first format display ratio, for example approximately 4x3. A video signal processor (301) asymmetrically compresses the second picture, for example 4:1 horizontally and 3:1 vertically. A video memory (420) stores lines of video of the asymmetrically compressed picture. Another video signal processor (300) combines portions of lines of video in the first video signal with the stored lines of video of the asymmetrically compressed picture for simultaneous display of the first and second pictures. The asymmetrically compressed second picture is displayed without aspect ratio distortion. The second picture can form an inset within the first picture. A single picture display can itself comprise a full screen of pictures from one source or from multiple sources.
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公开(公告)号:EP0532682A4
公开(公告)日:1993-12-01
申请号:EP91912590
申请日:1991-05-29
IPC分类号: H04N5/46 , G06F3/00 , G06T3/40 , G09G5/00 , G09G5/14 , G09G5/377 , G09G5/391 , H04N3/223 , H04N3/227 , H04N3/27 , H04N5/073 , H04N5/14 , H04N5/262 , H04N5/265 , H04N5/44 , H04N5/45 , H04N7/00 , H04N7/01 , H04N7/015 , H04N7/26 , H04N9/64 , H04N11/06 , H04N11/20 , H04N11/24
CPC分类号: H04N9/641 , G06T3/0012 , G06T3/4007 , H04N3/223 , H04N3/227 , H04N3/27 , H04N5/2624 , H04N5/45 , H04N7/007 , H04N7/01 , H04N7/0105 , H04N7/0122 , H04N7/015 , H04N9/64 , H04N19/90
摘要: A video display system comprises a first video signal source (304) of a first picture and a second video signal source of a second picture. A first signal processor (304) speeds up the first video signal. The second video signal (306) is vertically synchronized with the first video signal. The second video signal is delayed by a fraction of a field period in a field memory. A second signal processor (306) speeds up the synchronized second video signal. The first and second video signals are combined for side-by-side display of the pictures. If the first and second display format ratios are each approximately 4:3 and the third display format ratio is approximately 16:9, each of the side-by-side pictures can be displayed in a format display ratio of approximately 8:9. If each of the video signals is speeded up by approximately 4/3 and cropped horizontally by approximately 1/3, each of the side-by-side pictures is displayed substantially without aspect ratio distortion.
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