CIRCUIT D'AMPLIFICATION A COMMANDE DE GAIN EXPONENTIELLE
    1.
    发明授权
    CIRCUIT D'AMPLIFICATION A COMMANDE DE GAIN EXPONENTIELLE 失效
    具有指数增益控制放大器电路。

    公开(公告)号:EP0524294B1

    公开(公告)日:1995-11-22

    申请号:EP92905353.6

    申请日:1992-01-31

    IPC分类号: H03G1/04 H03G7/00

    CPC分类号: H03G1/04 H03G7/001

    摘要: The circuit comprises two identical amplifiers (A1, A2), the first being the basic amplification cell of the circuit (input Ie, output Is), and the second recieving a reference signal (Iref). The output of the second amplifier, which is the product of the input (Iref) and the gain (G), is an input of an amplifier gain (G) control loop. This loop receives a reference voltage (Vc) to set the gain (G) as an exponential function of Vc. A high gain differential amplifier (AD) is the main component in this loop. The voltage differential between its inputs tends to be maintained at zero by the control loop. According to the invention, a logarithmic transfer function (LTF) component is placed in the loop between the output of the second amplifier (A2) and the input of the high gain differential amplifier (AD).

    CIRCUIT D'ECHANTILLONNAGE DE SIGNAUX ANALOGIQUES
    2.
    发明授权
    CIRCUIT D'ECHANTILLONNAGE DE SIGNAUX ANALOGIQUES 失效
    抽样模拟信号。

    公开(公告)号:EP0513124B1

    公开(公告)日:1994-03-16

    申请号:EP91903535.2

    申请日:1991-01-25

    IPC分类号: G11C27/02

    CPC分类号: G11C27/024 G11C27/026

    摘要: A sampling circuit is described which aims to obtain a sampled and held signal level determined in relation to a well-defined reference level VO even though the input signal is a wanted signal referenced to a barely stable reference level. This is particularly the case when sampling signals from charge-transfer photosensitive devices for which the obscurity level can vary. The structure includes a sample and hold (EB1) and a capacitor (C1) input, with a resetting circuit which periodically charges the capacitor (C1) to a value which is roughly equal to the difference between the input reference level (variable) and the output reference level (constant). The resetting circuit includes a looped amplifier (AD1) in which the loop (B1, EB2, B2) is designed to introduce a voltage level shift which is equal to the shift intrinsically introduced by the sample and hold (B1, EB1, B2).