公开(公告)号：EP4420121A1

公开(公告)日：2024-08-28

申请号：EP22884753.9

申请日：2022-10-24

Applicant: Tachyum Ltd.

Inventor： DANILAK, Radoslav ,  MULLENDORE, Rodney ,  RADKE, William ,  TO, Chi

IPC: G11C5/02 ,  H05K3/36 ,  G11C8/12

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/025 ,  H05K2201/1015920130101 ,  H05K2201/1051520130101

公开(公告)号：EP3979070A1

公开(公告)日：2022-04-06

申请号：EP21210262.8

申请日：2019-08-15

Applicant: Tachyum Ltd.

Inventor： DANILAK, Radoslav

IPC: G06F8/41 ,  G06F9/38

Abstract: A methodology for populating an instruction word for simultaneous execution of instruction operations by a plurality of arithmetic logic units, ALUs), in a data path includes creating a dependency graph of instruction nodes, and initially designating any in the dependency graph as global, whereby the corresponding instruction node is expected to require inputs from outside of a predefined limited physical range of ALUs smaller than the full extent of the data path. A first available instruction node is selected from the dependency graph and assigned to the instruction word. Also selected are any available instruction nodes that are dependent upon a result of the first available instruction node and do not violate any predetermined rule, including that the instruction word may not include an available dependent instruction node designated as global. Available dependent instruction nodes are assigned to the instruction word, and the dependency graph updated to remove any assigned nodes from further assignment consideration.

公开(公告)号：EP3837599A1

公开(公告)日：2021-06-23

申请号：EP19849863.6

申请日：2019-08-15

Applicant: Tachyum Ltd.

Inventor： DANILAK, Radoslav

IPC: G06F9/00 ,  G06F9/30 ,  G06F15/00 ,  G06T1/60 ,  G09G5/36

公开(公告)号：EP4040290A1

公开(公告)日：2022-08-10

申请号：EP22165627.5

申请日：2019-08-15

Applicant: Tachyum Ltd.

Inventor： DANILAK, Radoslav

IPC: G06F8/41 ,  G06F9/38

Abstract: A processor having a plurality of arithmetic logic units, ALUs, that includes a sub-group of first, second and third ALUs, the sub-group at least partially defining a locally predefined range smaller than the plurality of ALUs. The first, second and third ALUs are arranged in a particular configuration in respect of their respective sides and the logical connections of their respective inputs and outputs. The processor has a clock speed that is too fast to guarantee execution, within a single clock cycle, of a combination of: (a) a most time-consuming process that could be performed by any of the first, second and/or third ALUs, and (b) receive a needed input, for performing the most time-consuming process, from an ALU of the processor that is outside of the locally predefined range.