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公开(公告)号：EP3945581A1
公开(公告)日：2022-02-02
申请号：EP21188315.2
申请日：2021-07-28
IPC分类号： H01L27/11551 , H01L27/11578 , H01L29/66 , H01L29/786 , H01L27/11597
摘要： A memory device includes transistor structures and memory arc wall structures. The memory arc wall structures are embedded in the transistor structures. The transistor structure includes a dielectric column, a source electrode and a drain electrode, a gate electrode layer and a channel wall structure. The source electrode and the drain electrode are located on opposite sides of the dielectric column. The gate electrode layer is around the dielectric column, the source electrode, and the drain electrode. The channel wall structure is extended from the source electrode to the drain electrode and surrounds the dielectric column. The channel wall structure is disposed between the gate electrode layer and the source electrode, between the gate electrode layer, and the drain electrode, and between the gate electrode layer and the dielectric column. The memory arc wall structure is extended on and throughout the channel wall structure.
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2.发明公开
公开(公告)号：EP3945583A1
公开(公告)日：2022-02-02
申请号：EP21188312.9
申请日：2021-07-28
IPC分类号： H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11587 , H01L27/11595 , H01L27/11597
摘要： A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.
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公开(公告)号：EP3945596A1
公开(公告)日：2022-02-02
申请号：EP21188314.5
申请日：2021-07-28
IPC分类号： H01L29/66 , H01L29/786 , H01L27/11551 , H01L27/11578
摘要： Amemory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.
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