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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
    1.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE 审中-公开

    公开(公告)号：EP3945584A3

    公开(公告)日：2022-02-16

    申请号：EP21188820.1

    申请日：2021-07-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： YOUNG, Bo-Feng ,  YEONG, Sai-Hooi ,  CHUI, Chi On ,  LIN, Yu-Ming

    IPC分类号： H01L27/11578 ,  H01L27/11597 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792

    摘要： 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
    2.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE 审中-公开

    公开(公告)号：EP3945584A2

    公开(公告)日：2022-02-02

    申请号：EP21188820.1

    申请日：2021-07-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： YOUNG, Bo-Feng ,  YEONG, Sai-Hooi ,  CHUI, Chi On ,  LIN, Yu-Ming

    IPC分类号： H01L27/11578 ,  H01L27/11597 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792

    摘要： 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

    SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MEMORY AND METHODS OF FORMING THE SAME
    3.
    发明公开
    SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MEMORY AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：EP3958313A1

    公开(公告)日：2022-02-23

    申请号：EP21188783.1

    申请日：2021-07-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： WANG, Chenchen Jacob ,  YEONG, Sai-Hooi ,  CHUI, Chi On ,  LIN, Yu-Ming

    IPC分类号： H01L27/06 ,  H01L27/1159 ,  H01L21/28

    摘要： A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.