公开(公告)号：EP1668853B1

公开(公告)日：2017-07-05

申请号：EP03818892.6

申请日：2003-09-30

申请人： Telecom Italia S.p.A.

发明人： D'AMICO, Valeria ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  RUSCITTO, Alfredo

IPC分类号： H04L25/02

CPC分类号： H04L25/0204 ,  H04L25/0206 ,  H04L25/0232 ,  H04L25/0236

公开(公告)号：EP1561288B1

公开(公告)日：2008-03-19

申请号：EP02787696.0

申请日：2002-11-15

申请人： Telecom Italia S.p.A. ,  STMicroelectronics S.r.l.

发明人： ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  OSSOLI, Alessandro ,  RUSCITTO, Alfredo

IPC分类号： H04B1/707

CPC分类号： H04B1/7093 ,  H04B1/7113 ,  H04B1/7117 ,  H04B2201/70707

摘要： A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffer (16), each addressing operation corresponding to a new correlation operation of the basic correlator (32) for the computation of a new value of the channel delay profile energy (DP(l)).

公开(公告)号：EP1668853A1

公开(公告)日：2006-06-14

申请号：EP03818892.6

申请日：2003-09-30

申请人： Telecom Italia S.p.A.

发明人： D'AMICO, Valeria ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  RUSCITTO, Alfredo

IPC分类号： H04L25/02

CPC分类号： H04L25/0204 ,  H04L25/0206 ,  H04L25/0232 ,  H04L25/0236

摘要： A system for estimating the transfer function of a transmission channel such as the downlink channel in a CDMA system over which a pilot signal (P-CPICH) and a data signal (DPCH) are transmitted. The system includes: - at least one estimator (21, 22, 27; 24, 23, 25) for producing first and second channel estimates from the pilot signal and the data signals, and - a combination node (26) for combining the first and second channel estimates to obtain final combined channel estimates. The system includes an interpolator module (25) adapted for interpolating the second channel estimates over a basic estimation reference time (T) to produce equal numbers of channel estimates over the basic estimation reference time (T) derived from the data signal and the pilot signal respectively, and, possibly - rate adaptation modules (23, 27) adapted for mapping the channel estimates on the basic estimation reference time (T). The combination node is a summation node (26) producing the final combined channel estimates as a sum (26) of the first channel estimates and the interpolated second channel estimates.

摘要翻译： 一种用于估计传输信道的传递函数的系统，例如在其中发送导频信号和数据信号的CDMA系统中的下行链路信道。 该系统包括用于从导频信号和数据信号产生第一和第二信道估计的至少一个估计器，以及用于组合第一和第二信道估计以获得最终组合信道估计的组合节点。 该系统包括内插器模块，其适于在基本估计参考时间上内插第二信道估计，以分别在从数据信号和导频信号导出的基本估计参考时间上产生相等数量的信道估计，并且可能的速率适应模块 在基本估计参考时间上映射信道估计。 组合节点是产生作为第一信道估计和内插的第二信道估计之和的最终组合信道估计的求和节点。

公开(公告)号：EP1561288A1

公开(公告)日：2005-08-10

申请号：EP02787696.0

申请日：2002-11-15

申请人： Telecom Italia S.p.A. ,  STMicroelectronics S.r.l.

发明人： ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  OSSOLI, Alessandro ,  RUSCITTO, Alfredo

IPC分类号： H04B1/707

CPC分类号： H04B1/7093 ,  H04B1/7113 ,  H04B1/7117 ,  H04B2201/70707

摘要： A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffer (16), each addressing operation corresponding to a new correlation operation of the basic correlator (32) for the computation of a new value of the channel delay profile energy (DP(l)).