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    Methods for forming single Damascene via or trench cavities and for forming dual Damascene via cavities
    3.
    发明公开
    Methods for forming single Damascene via or trench cavities and for forming dual Damascene via cavities 审中-公开
    单镶嵌孔或沟槽和双镶嵌孔的制备

    公开(公告)号：EP1427012A3

    公开(公告)日：2008-08-06

    申请号：EP03104553.7

    申请日：2003-12-04

    申请人： Texas Instruments Incorporated

    发明人： Jiang, Ping ,  Kraft, Robert ,  Xing, Guoqiang ,  Kirmse, Karen ,  Zielinski, Eden

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/76802

    摘要： Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching (112) a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming (104) an etch-stop layer over an existing interconnect structure, forming (106) a dielectric layer over the etch-stop layer, etching (114b) a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching (116) the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.

    Methods for forming single Damascene via or trench cavities and for forming dual Damascene via cavities
    4.
    发明公开
    Methods for forming single Damascene via or trench cavities and for forming dual Damascene via cavities 审中-公开
    单镶嵌孔或沟槽和双镶嵌孔的制备

    公开(公告)号：EP1427012A2

    公开(公告)日：2004-06-09

    申请号：EP03104553.7

    申请日：2003-12-04

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Jiang, Ping ,  Kraft, Robert ,  Xing, Guoqiang ,  Kirmse, Karen ,  Zielinski, Eden

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/76802

    摘要： Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching (112) a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming (104) an etch-stop layer over an existing interconnect structure, forming (106) a dielectric layer over the etch-stop layer, etching (114b) a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching (116) the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.

    摘要翻译： 方法是圆盘游离缺失用于形成沟槽或过孔在一个单一的镶嵌互连结构的空腔，其包括蚀刻（112）的介电层，以有形成空腔并暴露到下面的蚀刻停止层，以及腐蚀露出的蚀刻阻挡层，以延长 腔，并在现有互连结构暴露出导电特征，worin蚀刻所述电介质层的部分和蚀刻所述蚀刻停止层的暴露部分与基本上没有中间处理之间有步骤同时执行。 所以游离缺失光盘是在一个双镶嵌互连结构通过腔形成一个，包括形成（104）到蚀刻停止层上的现有互连结构，形成（106）在所述蚀刻停止层的介电层，蚀刻的方法（114B） 该介电层的一部分，以形成经由空腔的电介质层中并且暴露蚀刻阻挡层的（116）的部分，并且蚀刻该蚀刻停止层通过空腔，其中，所述电介质层在覆盖延长 蚀刻停止层的蚀刻。