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公开(公告)号：EP1797564A1
公开(公告)日：2007-06-20
申请号：EP05784116.5
申请日：2005-09-21
IPC分类号： G11C11/22
摘要： In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing the method of the invention comprises a first amplifier stage (Al) with an integrator circuit (715) and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit (725), and a sampling capacitor (720) connected between an output (716) of the first amplifier stage (Al) and an input (722) of the second amplifier stage (A2).
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3.发明公开
公开(公告)号：EP1719136A1
公开(公告)日：2006-11-08
申请号：EP05710941.5
申请日：2005-02-07
发明人： KARLSSON, Christer , HAMBERG, Per , BJÖRKLID, Staffan , THOMPSON, Michael, O. , WOMACK, Richard
CPC分类号： G11C11/22
摘要： In a method for operating a passive matrix-addessable ferroelectric or electret memory device comprising memory cells in the form of a ferroelectric or electret thin-film polarizable memory material exhibiting hysteresis, particularly a ferroelectric or electret polymer thin film, and a first set of parallel electrodes forming word line electrodes in the device and a second set of parallel electrodes forming bit lines in the device, the word lines being oriented orthogonally to the bit lines, such that the word lines and bit lines are in direct contact with the memory cells, which can be set to either of two polarization states or switched between these by applying a switching voltage larger than a coercive voltage of the memory material between a word line and a bit line, a voltage pulse protocol with at least one disturb generating operation cycle is applied for switching selected addressed cells to determined polarization state. The voltage pulse protocol further comprises a pre-disturb and/or post-disturb cycle before and after the disturb generating operation cycle respectively in order to minimize the effect of disturb voltages on non-addressed memory cells, when such voltages are generated thereto in the operation cycle when it is applied for either a write or read operation.
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公开(公告)号：EP1316090B1
公开(公告)日：2005-03-09
申请号：EP01985301.9
申请日：2001-08-24
IPC分类号： G11C5/00
CPC分类号： G11C7/1006 , G11C7/06 , G11C11/22
摘要： In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis between first and second sets (14; 15) of addressing electrodes, the electrodes of the first set (14) are word lines (WL) and the electrodes of the second set (15) are bit lines (BL) of the memory device. A memory cell (13) with a capacitor-like structure is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segment sharing and being defined by adjoining bit lines (BL) and means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BK) in order to determine a logical value stored in a memory cell (13) defined by the bit line (BL). In a readout method for a memory device of this kind a word line (WL) of a segment (S) is activated according to a protocol by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of a segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26). Use in a volumetric data storage apparatus with a plurality of stacked layers which each comprises a non-volatile passive matrix memory device.
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公开(公告)号：EP1316090A2
公开(公告)日：2003-06-04
申请号：EP01985301.9
申请日：2001-08-24
IPC分类号： G11C5/00
CPC分类号： G11C7/1006 , G11C7/06 , G11C11/22
摘要： In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis between first and second sets (14; 15) of addressing electrodes constituting word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) each segment sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit lines (BL) of a segment (S) with a sensing means (26) enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logicalvalue. In a readout method,a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of a segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26).
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