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22 条记录 (耗时 0.013 秒)

    Self-calibrated clock and timing signal generator
    3.
    发明公开
    Self-calibrated clock and timing signal generator 无效
    自动校准的时钟信号的时钟发生器和发生器。

    公开(公告)号：EP0103404A2

    公开(公告)日：1984-03-21

    申请号：EP83304638.6

    申请日：1983-08-11

    申请人： XEROX CORPORATION

    发明人： Bell, Alan G. ,  Lyon, Richard F. ,  Borriello, Gaetano

    IPC分类号： H03L7/06 ,  H03K5/15

    CPC分类号： H03L7/0805 ,  H03K3/0315 ,  H03K5/15 ,  H03L7/0891 ,  H03L7/0995

    摘要： A self-calibrated clock and timing signal generator provides reliable and continuous arbitrary digital waveforms of preselectable edge resolution. The generator comprises a multistage means (16) to produce a time-delayed signal of preselectable edge resolution and having a plurality of series-connected delay stages (6Q). The delays per stage are substantially identical so that the selection of any one of the outlets is representative of a predetermined amount of delay provided to an input signal to the multistage means. Calibrating means is integrally included to develop a control signal which is coupled to each of the stages of the multistage means to continuously maintain the predetermined amount of delay per stage. In the embodiment described, the calibrating means takes the form of an automatic frequency control (AFC) loop (12) wherein the frequency of a voltage controlled oscillator (VCO) (18) is regulated to be equal to that of a reference frequency. The VCO comprises a plurality of series-connected delay stages (30). The control voltage is applied to each stage to control the period or frequency of the VCO. The control voltage developed to adjust the VCO frequency is also employed to regulate the delay of the stages (60) comprising the multistage means. The stages of the delay line are identical in construction to the stages of the VCO.

    A switching network
    5.
    发明公开
    A switching network 失效
    Koppelnetz。

    公开(公告)号：EP0571166A2

    公开(公告)日：1993-11-24

    申请号：EP93303807.7

    申请日：1993-05-17

    申请人： XEROX CORPORATION

    发明人： Lyles, Joseph B. ,  Bell, Alan G.

    IPC分类号： H04L12/56

    CPC分类号： H04L12/5601 ,  H04L49/107 ,  H04L49/1561 ,  H04L49/203 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04Q11/0478

    摘要： A switching network having a sorting network (42) followed by a plurality of routing networks (43,44) for routing data packets from a plurality of inputs to a plurality of outputs includes a reservation ring mechanism (46) for resolving conflicts among inputs contending for access to specified ones of said outputs. This reservation ring mechanism (46) comprises means (76,78) for performing a sequence of step and compare operations in top-to-bottom ring-like order during at least one arbitration cycle for granting contending inputs access to said specified outputs in top-to-bottom order, with a maximum permissible plural number of contenders being given access to such an output on each of said arbitration cycles whenever there still are at least said that number of contenders in contention for that particular output.

    摘要翻译： 具有排序网络（42）的交换网络，随后是用于将数据分组从多个输入路由到多个输出的多个路由网络（43,44），包括：用于解决竞争的输入之间的冲突的预约环机制（46） 用于访问指定的所述输出。 该预留环机制（46）包括用于在至少一个仲裁周期期间以从顶到底的环状顺序执行步骤和比较操作的顺序的装置（76,78），用于授权竞争输入访问顶部的所述指定输出 每个所述仲裁周期中允许的最多许多竞争者允许多个竞争者获得这样的输出，只要至少说该数量的竞争者争用该特定输出。

    Computer-implemented system and method for parking reservations
    7.
    发明公开
    Computer-implemented system and method for parking reservations 审中-公开
    计算机辅助系统和VerfahrenfürParkreservierungen

    公开(公告)号：EP2444924A1

    公开(公告)日：2012-04-25

    申请号：EP11184253.0

    申请日：2011-10-07

    申请人： Xerox Corporation ,  Palo Alto Research Center Incorporated

    发明人： Stefik, Mark J. ,  Bell, Alan G. ,  Eldershaw, Craig ,  Good, Lance E. ,  Greene, Daniel H. ,  Torres, Francisco E. ,  Uckun, Serdar ,  Cummins, David P. ,  Partridge, Kurt ,  Glasnapp, James ,  Isaacs, Ellen ,  Krivacic, Robert T. ,  Hoover, Roger Phylos

    IPC分类号： G06Q10/02

    CPC分类号： G06Q10/02 ,  G06Q30/02 ,  G06Q30/08 ,  G07B15/02 ,  G08G1/142 ,  G08G1/147

    摘要： A computer-implemented system and method for offering merchant and shopper-friendly parking reservations through validated parking is provided. Motor vehicle parking spaces are managed through a server (11). Smart parking devices (13) and vehicle occupancy sensors (14) are interfaced to the server (11). Use of the parking space is managed. Occupancy of one of the parking spaces by a motor vehicle is sensed through the nearest vehicle occupancy sensor and the location of the parking space is provided to the server. An identity of the driver of the motor vehicle is determined through the nearest smart parking device and the identity of the driver is provided to the server. Use of the parking space is validated. The parking space's location and the driver's identity are retrieved at the location of a merchant. Payment for at least part of the use of the parking space from the merchant is provided through the server.

    摘要翻译： 提供一种用于通过验证停车提供商家和购物者友好的停车预约的计算机实现的系统和方法。 汽车停车位通过服务器（11）进行管理。 智能停车设备（13）和车辆占用传感器（14）被连接到服务器（11）。 使用停车位进行管理。 通过最近的车辆占用传感器感测到机动车辆的其中一个停车位的占用，并且将停车位的位置提供给服务器。 通过最近的智能停车设备确定机动车辆的驾驶员的身份，并且向服务器提供驾驶员的身份。 停车位的使用被验证。 停车位的位置和司机的身份在商家的地点检索。 通过服务器提供至少部分从商家使用停车位的付款。

    Switching system
    9.
    发明公开
    Switching system 失效
    交换系统

    公开(公告)号：EP0744879A3

    公开(公告)日：1999-04-21

    申请号：EP96303576.1

    申请日：1996-05-20

    申请人： XEROX CORPORATION

    发明人： Lyles, Joseph B. ,  Bell, Alan G.

    IPC分类号： H04Q11/04

    CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1546 ,  H04L49/1576 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A crossbar switching fabric for routing data packets in an ATM switch (10). A logic unit (13) associated with a reservation ring (12) in an ATM switch (10) intercepts data exiting a selected evaluator of the reservation ring (12), and processes this data to set-up a crossbar switching fabric for routing data packets of the ATM switch (10). The set-up data may be passed to the crossbar switching fabric upon each clock cycle thereby not incurring any pipeline processing delays. Alternatively, the set-up data is accumulated and stored in the logic unit (13) until the completion of an arbitration session, whereafter it is sent to the crossbar. In place of the logic unit (13) a plurality of registers may be added to each of the evaluators of the reservation ring. The registers in turn interconnected to each other in a shift register arrangement to provide the set-up data to the crossbar fabric.

    Data and clock recovery system for data communication controller
    10.
    发明公开
    Data and clock recovery system for data communication controller 失效
    用于数据传输控制装置的数据和时钟恢复系统。

    公开(公告)号：EP0104761A2

    公开(公告)日：1984-04-04

    申请号：EP83304859.8

    申请日：1983-08-23

    申请人： XEROX CORPORATION

    发明人： Borriello, Gaetano ,  Lyon, Richard F. ,  Bell, Alan G.

    IPC分类号： H04L25/49

    CPC分类号： H03L7/0995 ,  H03L7/0805 ,  H04L7/0041 ,  H04L7/0337 ,  H04L25/4904

    摘要： A data and clock recovery system is provided in the signal handling receiver (SHRx) stage of an integrated MOS circuit data communication controller (16) to provide accurate sampling of an incoming data packet for recovery of the data and data clock, regardless of differences in the electrical and environmentally affected characteristics of the circuit elements comprising the integrated MOSNLSI semiconductor chip. The system comprises a delay means (46) including a plurality of delay stages (90) to generate a transition pulse for every transition in the data packet, a similar delay means (48) to apply a predetermined amount of unit delay to all of the transition pulses, both data transition pulses and between-bit transition pulses, means (101,114) to develop a mask from the delayed transition pulses representative of the time occurrence of any between-bit transitions, means (112) to apply the mask to the incoming data packet whereby the extraneous between-bit transition pulses are removed therefrom, and means (42) coupled to the delay means to calibrate the delay means by ensuring that each of its delay stages continuously imposes a predetermined unit delay per stage.