公开(公告)号：EP0757450A3

公开(公告)日：2000-06-21

申请号：EP96112313.0

申请日：1996-07-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

摘要： The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.

摘要翻译： 本发明的目的是提供一种与传统电路相比大大降低电力消耗的滤波器电路，以及以足够高的速度实现第一次采集。 在根据本发明的滤波器电路中，并行使用匹配滤波器和滑动相关器，第一采集和保持由匹配滤波器执行，相关操作由滑动相关器执行，并且停止电压以供应 到匹配的过滤器。

公开(公告)号：EP0786733A2

公开(公告)日：1997-07-30

申请号：EP97101295.0

申请日：1997-01-28

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X i corresponding to each clement of the first input data string is input to capacitance switching circuits 10 1 to 10 n through input terminals 1 1 to 1 n . m bit of digital control data A i corresponding to each element of the second input data string are input to each capacitance switching circuit 10 i , and each bit a j of the control signal A j is input to the corresponding multiplexer circuit 6 ij . In the multiplexer circuit 6 ij , the capacitances C ij corresponding to the value of each bit of the control signal a j are connected to the input terminal 1 i or the reference charge V STD . The voltages corresponding to the products of inputted analog voltages X i and the control signals A i are outputted from each capacitance switching circuit 10 i . The output voltages of each capacitance switching circuit 10 i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

摘要翻译： 执行乘法，包括通过少量硬件高速累积。 对应于第一输入数据串的每个部分的模拟电压Xi通过输入端子11至1n输入到电容切换电路101至10n。 对应于第二输入数据串的每个元件的数字控制数据Ai的m位被输入到每个电容切换电路10i，并且控制信号Aj的每个位aj被输入到相应的多路复用器电路6ij。 在多路复用器电路6ij中，与控制信号aj的每个位的值对应的电容Cij连接到输入端1i或参考电荷VSTD。 从各电容切换电路10i输出与输入的模拟电压Xi和控制信号Ai的乘积对应的电压。 每个电容切换电路10i的输出电压被并联地输入到由反馈电容Cf连接的运算放大器3，并且从运算放大器3输出输入电压的和。另一方面，为了提供乘法 具有高计算速度的电路，而不降低计算精度和电路密度，根据本发明的乘法电路具有MOS开关或MOS多路复用器，其MOS具有宽度和长度的栅极，使得由输入电容定义的时间常数 并且开关等是恒定的。

公开(公告)号：EP0422659B1

公开(公告)日：1997-01-15

申请号：EP90119532.1

申请日：1990-10-11

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Takatori, Sunao ,  Kumagai, Ryohei ,  Matsumoto, Koji ,  Yamamoto, Makoto

IPC分类号： G06F15/80

CPC分类号： G06N3/063

公开(公告)号：EP0584688A3

公开(公告)日：1994-04-06

申请号：EP93113106.4

申请日：1993-08-16

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size. The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
   iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

公开(公告)号：EP0584688A2

公开(公告)日：1994-03-02

申请号：EP93113106.4

申请日：1993-08-16

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.
The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
   iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

摘要翻译： 本发明的一个目的是提供一种不需要刷新，其电路尺寸小的存储器件。 该存储器件具有一个存储单元“MC”，该存储单元包括：i）具有通过保护电阻“R1”接地的输入电压“Vi”和源“S1”接地的栅极“G1”的P沟道第一FET; ii）具有连接到第一FET的漏极“D1”的栅极“G2”，连接到电源“Vcc”的漏极“D2”和连接到栅极的源极“S2”的N沟道的第二FET 第一个FET的“G1”通过保护电阻“R2”; 和iii）连接第二FET的栅极“G2”和电源“Vcc”的开关“SWR”。 自保持电路由一对FET形成。

公开(公告)号：EP0450521A2

公开(公告)日：1991-10-09

申请号：EP91105033.4

申请日：1991-03-28

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G06F15/80

CPC分类号： G06N3/082

摘要： A learning method for a data processing system comprising an input layer and output layer which comprises a plurality of neurons each of which outputs an predetermined data after igniting according to the predetermined processing results performed onto an input data, and an middle layer, arranged between the input and output layer, the middle layer comprising a plurality of neurons each of which is connected to each neuron of the input and output layer; characterized in the following steps: the ignition patterns of the input layer and the output layer are determined artificially according to a plurality of inputs and outputs; weights of synapses of the middle layer and the output layer are increased so as to obtain the tendency that the ignition pattern of middle layer becomes the nearest approximation to the ignition patterns of input layer and output layer according to each input and output; the same processings as above are performed with respect to all inputs and outputs.

摘要翻译： 一种用于数据处理系统的学习方法，包括输入层和输出层，其包括多个神经元，每个神经元根据对输入数据执行的预定处理结果在点燃之后输出预定数据，以及中间层，布置在 输入和输出层，中间层包括多个神经元，每个神经元连接到输入和输出层的每个神经元; 其特征在于以下步骤：根据多个输入和输出人工确定输入层和输出层的点火模式; 中间层和输出层的突触重量增加，以获得根据每个输入和输出中间层的点火模式与输入层和输出层的点火模式近似近似的趋势; 对于所有输入和输出执行与上述相同的处理。

公开(公告)号：EP0405174A2

公开(公告)日：1991-01-02

申请号：EP90110384.6

申请日：1990-05-31

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Takatori, Sunao ,  Kumagai, Ryohei ,  Yamamoto, Makoto ,  Matsumoto, Koji

IPC分类号： G06F15/80

CPC分类号： G06N3/08

摘要： An adaptation method for a data processing system comprising a plurality of neurons each of which outputs an output according to a comparison between a sum of multiplied inputs by weights and a threshold, characterized in the following steps:
The threshold of the neuron which has generated significant output at certain point of time is compulsorily increased to a maximal value;
The weight of the neuron is adapted for a constant value of the inputs; and the threshold is decreased to a value at the point.

摘要翻译： 一种用于数据处理系统的适应方法，包括多个神经元，每个神经元根据权重和相乘输入之和之间的比较来输出输出，其特征在于以下步骤：产生显着的神经元的阈值 在某个时间点的输出强制增加到最大值; 神经元的权重适用于输入的恒定值; 并且阈值减小到该点处的值。

公开(公告)号：EP0855796A3

公开(公告)日：2002-07-31

申请号：EP98101319.6

申请日：1998-01-26

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Zhou, Changming ,  Yamamoto, Makoto ,  Zhou, Xuping ,  Takatori, Sunao ,  Qin, Xiaoling

IPC分类号： H03H17/02

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： The invention provides according to a first aspect a low electric power consumption matched filter. The signal received at an input terminal is input to a shift-register having stages equal to the spread code length number after conversion into M-bit digital signals in an analog-to-digital converter. The outputs of the shift-register stages are input to EXCLUSIVE-OR circuits set corresponding to each stage, so that EXCLUSIVE-OR is performed between the outputs and corresponding spread code bits d 1 to d N . The outputs of the EXCLUSIVE-OR circuits are analogously added in an analog adder and output from an output terminal. According to a second aspect the invention provides a filter circuit using an analog operation circuit to prevent lowering of operation accuracy caused by the residual charge. Input analog signals successively undergo sampling and holding in each sampling and holding circuit, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sampling and holding circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sampling and holding circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is set double and refreshed in the same way.

公开(公告)号：EP0707274B1

公开(公告)日：2000-05-03

申请号：EP95114823.8

申请日：1995-09-20

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： G06J1/00

CPC分类号： G06J1/00

公开(公告)号：EP0855796A2

公开(公告)日：1998-07-29

申请号：EP98101319.6

申请日：1998-01-26

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Zhou, Changming ,  Yamamoto, Makoto ,  Zhou, Xuping ,  Takatori, Sunao ,  Qin, Xiaoling

IPC分类号： H03H17/02

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： The invention provides according to a first aspect a low electric power consumption matched filter. The signal received at an input terminal is input to a shift-register having stages equal to the spread code length number after conversion into M-bit digital signals in an analog-to-digital converter. The outputs of the shift-register stages are input to EXCLUSIVE-OR circuits set corresponding to each stage, so that EXCLUSIVE-OR is performed between the outputs and corresponding spread code bits d 1 to d N . The outputs of the EXCLUSIVE-OR circuits are analogously added in an analog adder and output from an output terminal. According to a second aspect the invention provides a filter circuit using an analog operation circuit to prevent lowering of operation accuracy caused by the residual charge. Input analog signals successively undergo sampling and holding in each sampling and holding circuit, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sampling and holding circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sampling and holding circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is set double and refreshed in the same way.

摘要翻译： 本发明根据第一方面提供一种低功耗匹配滤波器。 在模数转换器中转换成M位数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级设置的EXCLUSIVE-OR电路，从而在输出和对应的扩展码位d1至dN之间执行EXCLUSIVE-OR。 EXCLUSIVE-OR电路的输出类似地添加到模拟加法器中并从输出端子输出。 根据第二方面，本发明提供一种使用模拟运算电路的滤波电路，以防止由剩余电荷引起的操作精度降低。 输入模拟信号在每个采样和保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并在加法电路中相加。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样和保持电路和乘法电路由模拟运算电路形成，并且每个包括用于消除剩余电荷的开关。 正常工作的采样和保持电路和乘法电路通过提供更换其功能的电路来顺序刷新。 加法电路设置为双倍并以相同的方式刷新。