公开(公告)号：EP0930723A3

公开(公告)日：2003-07-30

申请号：EP99100692.5

申请日：1999-01-14

申请人： Yozan Inc.

发明人： Zhou, Changming ,  Zhou, Xuping

IPC分类号： H04B1/707

CPC分类号： H04B1/70752 ,  H04B1/70735 ,  H04B1/70751 ,  H04B1/7077

摘要： A (direct-sequence code division multiple access) DS-CDMA cellular system includes a plurality of cells each having one base station and a plurality of mobile stations. A signal transmitted form the base station is distinguished by a long code which is different from the others being uniquely allocated to each cell. A long code synchronization timing being detected by a correlation using a common short code. The long codes are searched in each mobile station by a partial correlation in a timing according to the long code synchronization timing. The partial correlation is a correlation between a signal received and a segment of a code defined by a part of the long code, the part being shifted in the long code. Further, the long codes are classified into a plurality of long code groups defined by long code group identification codes. A delay profile of the long code group identification code is detected and is compensated in fading according to said short code. Then, the long code group identification code is combined by rake combining, and is demodulated.

公开(公告)号：EP0932262A3

公开(公告)日：2003-05-14

申请号：EP98124528.5

申请日：1998-12-22

申请人： Yozan Inc. ,  NTT DoCoMo, Inc.

发明人： Zhou, Changming ,  Zhou, Xuping ,  Sawahashi, Mamura ,  Adachi, Fumiyuka

IPC分类号： H04B1/707 ,  H03H17/02

CPC分类号： H04B1/707

摘要： A plurality of sets of spreading code sequences are stored in registers. In case of soft hand-over, multi-code and long-delay paths, it is possible that the correlation peaks derived by the different PN sequences overlap. The spreading code sequences then are shifted by the generator registers in order to separate the peaks by one or more chips.

公开(公告)号：EP0757450A3

公开(公告)日：2000-06-21

申请号：EP96112313.0

申请日：1996-07-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

摘要： The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.

摘要翻译： 本发明的目的是提供一种与传统电路相比大大降低电力消耗的滤波器电路，以及以足够高的速度实现第一次采集。 在根据本发明的滤波器电路中，并行使用匹配滤波器和滑动相关器，第一采集和保持由匹配滤波器执行，相关操作由滑动相关器执行，并且停止电压以供应 到匹配的过滤器。

公开(公告)号：EP0939500A2

公开(公告)日：1999-09-01

申请号：EP99103383.8

申请日：1999-02-22

申请人： Yozan Inc.

发明人： Zhou, Changming

IPC分类号： H04B1/707

CPC分类号： H04B1/7093 ,  H03H17/0254 ,  H04B1/708 ,  H04B2201/7071

摘要： An analog input signal is converted into digital data by an A/D converted, a digital multiplication as a correlation calculation is executed by a plurality of exclusive-OR circuits, and an analog addition of outputs of the exclusive-OR circuits is performed. In the multiplication, the digital data is multiplied a spreading code of one bit. The exclusive-OR outputs are added for each weight of bits, and the addition results are weighted and summed up.

摘要翻译： 通过A / D转换将模拟输入信号转换为数字数据，由多个异或电路执行相关计算的数字乘法，并执行异或电路的输出的模拟相加。 在乘法中，数字数据被乘以一位的扩展码。 对每个比特的权重添加异或输出，并对加法结果进行加权和归纳。

公开(公告)号：EP0868061A2

公开(公告)日：1998-09-30

申请号：EP98102521.6

申请日：1998-02-13

申请人： Yozan Inc.

发明人： Zhou, Xuping ,  Shou, Guoliang ,  Zhou, Changming

IPC分类号： H04L27/233

CPC分类号： H04L27/2331

摘要： A π/n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through π/4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by π/8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.

摘要翻译： 本发明的π/ n移位PSK解调器通过以下方法由数字逻辑装置形成。 XOR4通过从SH2输出的pi / 4移位QPSK和SH1的前一个输出计算当前样本之间的异或运算。 在第一操作装置5中从XOR4的输出中累积1，并将其乘以pi / 8获得当前和先前符号之间的绝对相位差。 来自SH1的前者或后面的四位从SH2的相应的前一个或后四位中减去，每个位的结果被相加，并且其符号被加到符号加法装置10中的绝对相位数据。在相位偏移为 从10的输出中减去，在判断电路13中解调为原来的。

公开(公告)号：EP0853388A2

公开(公告)日：1998-07-15

申请号：EP98100151.4

申请日：1998-01-07

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Zhou, Changming ,  Zhou, Xuping

IPC分类号： H04B1/707 ,  H04B7/005

CPC分类号： H04B1/711 ,  H04B1/7093 ,  H04B1/7117 ,  H04B7/01 ,  H04B2201/70701

摘要： Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31 - 34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31 - 34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error. In this way, the correction vectors are sequentially modified based on the temporary determination results for the information symbols.

摘要翻译： 通过最小的电路以高精度校正扩频信号的相位。 接收机的相位校正电路31-34中的一个对应于每个路径。 解扩输出的I分量和Q分量被提供给相位校正电路31-34。相位误差提取器1从接收的导频块中提取第一相位误差。 相位校正器2使用已经基于第一相位误差计算的校正矢量来校正接收信息符号的相位误差。 RAKE合成器25将校正的接收信号与其他路径的相位校正电路的输出合成，并将该合成信号输出到暂时确定要处理的信息符号的临时确定器3。 使用临时确定结果在校正矢量修改器4中修改相位误差。 基于修正的相位误差计算新的校正矢量。 以这种方式，基于信息符号的临时确定结果，顺序修改校正矢量。

公开(公告)号：EP0874470A3

公开(公告)日：2003-04-16

申请号：EP98106808.3

申请日：1998-04-15

申请人： Yozan, Inc.

发明人： Zhou, Changming ,  Zhou, Xuping ,  Shou, Guoliang

IPC分类号： H04B1/16 ,  H04B1/40

CPC分类号： H04B1/1615 ,  H04W52/029 ,  Y02D70/40

摘要： A waiting circuit incorporated within a portable terminal of a mobile communication system, for detecting a predetermined signal from a base station so as to start other circuits in a sleep mode than the waiting circuit. The predetermined signal is generated in the base station at a speed of a predetermined symbol rate and modulated to be a intermediate frequency signal. The waiting circuit samples the intermediate frequency signal in response to a sampling clock of a speed of an integer times as quick as the symbol rate. The sampled signal is input to a matched filter for multiplying the sampled signal by a predetermined sequence of coefficients. This coefficients corresponds to the intermediate frequency signal sampled by the sub-sampling circuit.

公开(公告)号：EP0939500A3

公开(公告)日：2003-04-02

申请号：EP99103383.8

申请日：1999-02-22

申请人： Yozan Inc.

发明人： Zhou, Changming

IPC分类号： H04B1/707 ,  H03H17/02

CPC分类号： H04B1/7093 ,  H03H17/0254 ,  H04B1/708 ,  H04B2201/7071

摘要： An analog input signal is converted into digital data by an A/D converted, a digital multiplication as a correlation calculation is executed by a plurality of exclusive-OR circuits, and an analog addition of outputs of the exclusive-OR circuits is performed. In the multiplication, the digital data is multiplied a spreading code of one bit. The exclusive-OR outputs are added for each weight of bits, and the addition results are weighted and summed up.

公开(公告)号：EP0756378B1

公开(公告)日：2001-10-24

申请号：EP96112146.4

申请日：1996-07-26

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Zhou, Changming ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H03H11/04 ,  H03H17/02

CPC分类号： H03H11/04 ,  H03H17/0254

摘要： The present invention has an object to provide a matched filter with further reduced electric power. In a matched filter circuit according to the present invention, the electric power supply is stopped with respect to an unnecessary circuit according to an experience that signal is partially sampled just after the acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups"1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

公开(公告)号：EP1001534A2

公开(公告)日：2000-05-17

申请号：EP99113272.1

申请日：1999-07-08

申请人： Yozan Inc.

发明人： Zhou, Changming ,  Suzuki, Kunihiko ,  Tomatsu, Takashi ,  Fukui, Masataka

IPC分类号： H03K5/24 ,  H03M1/42

CPC分类号： H03M1/42

摘要： An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer of CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

摘要翻译： 模数转换器包括差分输入部分，其接收输入电压和参考电压，并且具有第一和第二输出端，连接到所述第一和第二输出端的正反馈部分，在其输入端连接的CMOSFET缓冲器， 第一输出端子，在其输入端连接到第二输出端子的第二缓冲器，以及比较电路，包括连接在第一和第二输出端子之间的第一开关部分，用于响应于比较来连接和断开第一和第二输出端子 时钟信号。 比较电路在其输出端连接到第一或第二缓冲器。 当所述切换部分响应于比较时钟信号而从连接状态变为断开状态时，比较输入电压和参考电压。