公开(公告)号：EP3121846B1

公开(公告)日：2018-03-21

申请号：EP16181064.3

申请日：2016-07-25

Applicant: NXP USA, Inc.

Inventor： Wood, Thomas

IPC: H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L23/544 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/6835 ,  H01L21/76892 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/544 ,  H01L27/0705 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).

公开(公告)号：EP3075010B1

公开(公告)日：2018-01-10

申请号：EP14815124

申请日：2014-11-13

Applicant: QUALCOMM INC

Inventor： LI XIA ,  KIM DAEIK DANIEL ,  YANG BIN ,  KIM JONGHAE ,  PERRY DANIEL WAYNE

IPC: H01L27/07 ,  G05F3/16 ,  H01L29/739

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

公开(公告)号：EP3075010A1

公开(公告)日：2016-10-05

申请号：EP14815124.4

申请日：2014-11-13

Applicant: Qualcomm Incorporated

Inventor： LI, Xia ,  KIM, Daeik Daniel ,  YANG, Bin ,  KIM, Jonghae ,  PERRY, Daniel Wayne

IPC: H01L27/07

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract translation: 一种方法包括：根据场效应晶体管（FET）型操作，偏置第一栅极电压以使单极性电流从晶体管的第一区域流过晶体管的第二区域。 该方法还包括偏置主体端子以使双极电流根据双极结型晶体管（BJT）型操作从第一区域流动到第二区域。 单极电流与双极电流同时流动，以提供互补金属氧化物半导体（CMOS）技术中的双模数字和模拟器件。

公开(公告)号：EP2251901A1

公开(公告)日：2010-11-17

申请号：EP07859821.6

申请日：2007-12-14

Applicant: Fujitsu Limited

Inventor： KATAKURA, Hiroshi

IPC: H01L21/822 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H03K19/00 ,  H03K19/003

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/088

Abstract: a semiconductor device in a continuous diffusion region formed on a semiconductor substrate and having either a P-type or N-type polarity includes: a first transistor formed within the continuous diffusion region; a second transistor formed within the continuous diffusion region and in an area that is different from an area where the first transistor is formed; a third transistor formed within the continuous diffusion region and in an area between the first and second transistors, and having a gate electrode to which a fixed potential is applied; and a fourth transistor formed within the continuous diffusion region and in an area between the second and third transistors, and having a gate electrode to which a fixed potential is applied.

Abstract translation: 在形成在半导体衬底上并且具有P型或N型极性的连续扩散区中的半导体器件包括：形成在连续扩散区内的第一晶体管; 第二晶体管，所述第二晶体管形成在所述连续扩散区域内且处于与形成所述第一晶体管的区域不同的区域中; 第三晶体管，形成在所述连续扩散区域内并且位于所述第一晶体管和所述第二晶体管之间的区域中，并且具有被施加固定电位的栅电极; 以及第四晶体管，其形成在所述连续扩散区域内并且位于所述第二晶体管和所述第三晶体管之间的区域中，并且具有被施加固定电位的栅电极。

公开(公告)号：EP2232539A2

公开(公告)日：2010-09-29

申请号：EP08861157.9

申请日：2008-12-16

Applicant: Micron Technology, INC.

Inventor： TRAN, Luan, C.

IPC: H01L21/336 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

公开(公告)号：EP2130228A1

公开(公告)日：2009-12-09

申请号：EP08730376.4

申请日：2008-02-21

Applicant: Micron Technology, Inc.

Inventor： GONZALEZ, Fernando ,  MOULI, Chandra, V.

IPC: H01L27/108 ,  H01L29/78 ,  G11C11/401 ,  H01L21/762 ,  H01L27/07

CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

Abstract: A capacitor-less floating-body memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell (82) in a active area of a substantially physically isolated portion of the bulk semiconductor substrate (10). A pass transistor (70) is formed on the active area for coupling with a word line (88). The capacitor-less memory cell further includes a read/write enable transistor (76) vertically configurated along at least one vertical side of the active area, sharing a floating source/drain region (80) with the pass transistor, and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

公开(公告)号：EP1307921A2

公开(公告)日：2003-05-07

申请号：EP01931006.9

申请日：2001-05-01

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KRISHNAN, Srinath

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L29/1041 ,  H01L29/7831 ,  H01L29/7841 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78645

Abstract: A MOSFET multiple device structure (50) is provided. The structure (50) comprises a plurality of MOSFET devices (52, 54, 56) sharing at least one heavily doped region (110) extending underneath a gate region (90, 156) of at least two of the plurality of MOSFET devices (52, 54, 56). The shared heavily doped region (110) provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the MOSFET devices (52, 54, 56) between a body region (120, 158) and the gate region (90, 156).

公开(公告)号：EP0144909B1

公开(公告)日：1992-07-22

申请号：EP84114414.0

申请日：1984-11-28

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Baliga, Bantval Jayant

IPC: H01L27/06 ,  H01L23/52

CPC classification number: H01L29/7802 ,  H01L23/522 ,  H01L27/0617 ,  H01L27/0705 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Hybrid power switching semiconductor devices advantageously integrate IGT and MOSFET structures. The IGT and MOSFET portions of the overall device include respective gate structures each having an associated gate electrode capacitance, and the hybrid device includes a resistance element connecting the IGT and MOSFET gates. The gate structures preferably comprise polysilicon electrodes, and the resistance element comprises a polysilicon bridge formed at the same time during device fabrication. The overall device has only a single gate terminal, which is connected relatively directly to one of the IGT and MOSFET gates, and indirectly through the resistance element to the other of the IGT and MOSFET gates such that an RC time delay network is defined. Two different types of power switching functions are achieved depending upon whether the overall device gate terminal is connected nearer the IGT gate or the MOSFET gate.

公开(公告)号：EP0144909A3

公开(公告)日：1987-05-27

申请号：EP84114414

申请日：1984-11-28

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Baliga, Bantval Jayant

IPC: H01L27/06 ,  H01L23/52

CPC classification number: H01L29/7802 ,  H01L23/522 ,  H01L27/0617 ,  H01L27/0705 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Hybrid power switching semiconductor devices advantageously integrate IGT and MOSFET structures. The IGT and MOSFET portions of the overall device include respective gate structures each having an associated gate electrode capacitance, and the hybrid device includes a resistance element connecting the IGT and MOSFET gates. The gate structures preferably comprise polysilicon electrodes, and the resistance element comprises a polysilicon bridge formed at the same time during device fabrication. The overall device has only a single gate terminal, which is connected relatively directly to one of the IGT and MOSFET gates, and indirectly through the resistance element to the other of the IGT and MOSFET gates such that an RC time delay network is defined. Two different types of power switching functions are achieved depending upon whether the overall device gate terminal is connected nearer the IGT gate or the MOSFET gate.

公开(公告)号：EP1247300B1

公开(公告)日：2017-10-11

申请号：EP00980162.2

申请日：2000-11-07

Applicant: Cree, Inc.

Inventor： BAKOWSKI, Mietek ,  DAHLQUIST, Fanny ,  LENDENMANN, Heinz

IPC: H01L27/07 ,  H01L29/772 ,  H01L27/098 ,  H01L29/24 ,  H01L29/06 ,  H01L29/16 ,  H01L29/808

CPC classification number: H01L29/7722 ,  H01L27/0705 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/8083