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公开(公告)号：EP2936254A1
公开(公告)日：2015-10-28
申请号：EP13802669.5
申请日：2013-12-11
发明人： BONNET, Thierry , DALLA PIAZZA, Silvio , CHRISTE, Laurent , KLOPFENSTEIN, François , FLEURY, Emmanuel , GODAT, Yves , JEANNET, Nicolas
摘要： The present invention concerns an electronic watch comprising at least one electric motor (M1) for driving analogue display means, a timepiece module (12) comprising a time base (14) providing a clock signal (Sh) connected to a divider circuit (16), said divider circuit providing a reference signal sent to a control circuit (18) arranged to control said electric motor, characterised in that the timepiece module further comprises a measurement and correction circuit (26) arranged between the time base and the divider circuit and providing an intermediate signal (Si) and in that the time base, the compensation module, the divider circuit and the control circuit are arranged in the same housing (13) to form said timepiece module.
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2.发明公开
公开(公告)号：EP2784605A1
公开(公告)日：2014-10-01
申请号：EP13161356.4
申请日：2013-03-27
发明人： Bonnet, Thierry , Dalla Piazza, Silvio , Christe, Laurent , Klopfenstein, François , Fleury, Emmanuel , Godat, Yves , Jeannet, Nicolas
摘要： La présente invention concerne une montre électronique comprenant au moins un moteur électrique (M1) pour entraîner des moyens d'affichage analogiques, un module horloger (12) comprenant une base de temps (14) fournissant un signal d'horloge (Sh) connecté à un circuit diviseur (16), ledit circuit diviseur fournissant un signal de référence envoyé à un circuit de contrôle (18) agencé pour contrôler ledit moteur électrique.
Le module horloger comprend en outre un circuit de mesure et de correction (26) agencé entre la base de temps et le circuit diviseur et fournissant un signal intermédiaire (Si).
La base de temps, le module de compensation, le circuit diviseur et le circuit de contrôle sont agencés dans le même boîtier (13) pour former ledit module horloger.摘要翻译： 手表具有用于驱动模拟显示单元的电动机（M1）。 钟表模块（12）具有提供连接到分频器电路（16）的时钟信号（Sh）的时基（14）。 分频器电路提供被发送到布置成控制电动机的控制电路（18）的参考信号。 分频器电路和控制电路布置在相同的壳体（13）中以形成钟表模块。 止动表模块（30）连接到钟表模块。 秒表模块具有通过钟表模块的中间信号（Si）补偿的节奏。 还包括用于校准钟表制造模块的方法的独立权利要求。
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公开(公告)号：EP2406691A4
公开(公告)日：2012-08-01
申请号：EP10750268
申请日：2010-03-09
申请人： ALLEN VANGUARD CORP
CPC分类号： G04G3/04
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公开(公告)号：EP2406691A1
公开(公告)日：2012-01-18
申请号：EP10750268.4
申请日：2010-03-09
CPC分类号： G04G3/04
摘要： An apparatus is provided for generating a timing signal having an input for receiving a first signal indicating successive time intervals, means for receiving a second signal indicating successive time intervals, and a generator adapted to generate a timing signal based on the second signal and on a relationship between one or more time intervals of the first signal and one or more time intervals of the second signal. This arrangement enables a timing signal to be generated using a time signal produced by a source or device and to be based on a time signal produced by another source or device.
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公开(公告)号：EP1634373B1
公开(公告)日：2007-03-21
申请号：EP04732266.4
申请日：2004-05-12
发明人： RUFFIEUX, David
摘要： The invention relates to a time base comprising two oscillators, the frequency of one of which is lower than the other, the latter being intermittently attenuated, generating a first time reference (REF) with the same intermittence, stable by difference between the frequencies of the two oscillators, a second permanent time reference (RTC) being obtained by division of the frequency of the oscillator with the lowest frequency and the factor for the division being a function of the pulses counted for the first oscillator (OSC1) during a time interval determined by the first stable time reference (REF).
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公开(公告)号：EP3168695A1
公开(公告)日：2017-05-17
申请号：EP15194568.0
申请日：2015-11-13
摘要： Le procédé de test de la marche d'une montre électronique à dispositif base de temps (1) comprend trois étapes principales pour le test sur un équipement de test. Le dispositif base de temps comprend au moins un module horloger (2) avec un résonateur (3) lié à un oscillateur d'un circuit électronique (4), qui est suivi par un circuit diviseur, qui est commandé par un circuit d'inhibition, et qui fournit un signal divisé de cadencement d'un moteur. Dans une première étape, il est effectué une mesure de la fréquence d'un signal de référence de l'oscillateur dans au moins une période de mesure sans inhibition. Une deuxième étape est prévue pour acquérir la valeur d'inhibition actuelle pour inhiber un certain nombre d'impulsions d'horloge dans une période d'inhibition subséquente et déterminer la valeur d'inhibition. Finalement, une troisième étape est prévue pour calculer la fréquence correspondante de marche de la montre.
摘要翻译： 测试基于时计的电子表（1）的时间的方法包括三个主要步骤用于在测试设备上进行测试。 该时基装置包括至少一个具有链接到电子电路（4）的振荡器的谐振器（3）的钟表模块（2），其随后是分频器电路，该分频器电路由抑制电路 并提供电动机的分割定时信号。 在第一步骤中，在至少一个测量周期内进行振荡器的参考信号的频率的测量而不受抑制。 提供第二步骤以获取当前禁止值以抑制随后禁止周期中的多个时钟脉冲并确定禁止值。 最后，提供第三步来计算手表的相应运行频率。
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7.发明公开
公开(公告)号：EP2772822A1
公开(公告)日：2014-09-03
申请号：EP14156943.4
申请日：2014-02-27
发明人： Liu, Jinxiu , Guo, Shubao , Li, Ding
摘要： The present document discloses a correction circuit. The correction circuit includes a frequency dividing circuit (110), a frequency dividing coefficient operation circuit (120), a built-in temperature collection circuit (130), and a power-on and power-off detection circuit (140). The built-in temperature collection circuit (130) is configured to collect a temperature of the chip; the power-on and power-off detection circuit (140) is configured to detect power-on and power-off of the chip; the frequency dividing coefficient operation circuit (120) is configured to calculate, according to the temperature of the chip collected by the built-in temperature collection circuit (130) when the power-on and power-off detection circuit (140) detects that the chip is powered off, a frequency dividing coefficient, and output the frequency dividing coefficient to the frequency dividing circuit (110); and the frequency dividing circuit (110) is configured to provide, according to the frequency dividing coefficient output by the frequency dividing coefficient operation circuit, a timing pulse for a real-time clock (11).
摘要翻译： 本文件公开了一种校正电路。 校正电路包括分频电路（110），分频系数运算电路（120），内置温度采集电路（130）以及通电断电检测电路（140）。 内置的温度采集电路（130）被配置为收集芯片的温度; 上电断电检测电路（140）被配置为检测芯片的通电和断电; 分频系数运算电路（120）被配置为当电源接通和断电检测电路（140）检测到所述内部温度采集电路（130）检测到的所述内部温度采集电路（130）所收集的芯片的温度时， 芯片断电，分频系数，并将分频系数输出到分频电路（110）; 并且分频电路（110）根据由分频系数运算电路输出的分频系数，提供实时时钟（11）的定时脉冲。
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8.发明授权
公开(公告)号：EP1681608B1
公开(公告)日：2010-05-26
申请号：EP06003153.1
申请日：1998-03-03
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9.发明授权
公开(公告)号：EP0915409B1
公开(公告)日：2006-05-31
申请号：EP98905735.1
申请日：1998-03-03
CPC分类号： G04F5/10 , G04G3/04 , G04G19/00 , G05F1/468 , G05F1/56 , G05F1/618 , G05F3/242 , H03B5/36 , H03K3/011 , H03K3/0307 , H03K3/3545
摘要： A constant-voltage generating circuit (100) which generates a constant voltage. The circuit (100) incorporates a first voltage generating circuit (110) which generates a reference voltage, and a second voltage generating circuit (130) which generates the constant voltage having a specified correlation with the reference voltage. The first voltage generating circuit (110) incorporates a first constant-current source (150-1) which supplies a constant current and a first transistor (112) for controlling voltage which is supplied with the above-mentioned constant current and outputs the above-mentioned reference voltage set on the basis of a prescribed potential. The constant current is set at the value of the saturated operating area of the first transistor (112) for controlling voltage.
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公开(公告)号：EP1634373A1
公开(公告)日：2006-03-15
申请号：EP04732266.4
申请日：2004-05-12
发明人： RUFFIEUX, David
摘要： The invention relates to a time base comprising two oscillators, the frequency of one of which is lower than the other, the latter being intermittently attenuated, generating a first time reference (REF) with the same intermittence, stable by difference between the frequencies of the two oscillators, a second permanent time reference (RTC) being obtained by division of the frequency of the oscillator with the lowest frequency and the factor for the division being a function of the pulses counted for the first oscillator (OSC1) during a time interval determined by the first stable time reference (REF).
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