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    Dynamic random access memory (DRAM) semiconductor device
    4.
    发明公开
    Dynamic random access memory (DRAM) semiconductor device 无效
    Halbleiterbauelement mit dynamischem Arbeitsspeicher（DRAM）

    公开(公告)号：EP1640847A2

    公开(公告)日：2006-03-29

    申请号：EP05026720.2

    申请日：1991-04-16

    申请人： Rambus, Inc.

    发明人： Farmwald, Michael ,  Horowitz, Mark

    IPC分类号： G06F1/04

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present invention concerns a dynamic random access memory (DRAM) semiconductor device having at least one memory array which includes a plurality of memory cells arranged in rows and columns. The DRAM contains connection means adapted to connect the DRAM to an external bus which is a part of a semiconductor bus architecture. The semiconductor bus architecture includes a plurality of semiconductor devices connected in parallel to the external bus. The external bus includes a plurality of bus lines for carrying substantially all address, data, and control information needed by the DRAM for communication with substantially every other semiconductor device connected to the external bus. The connection means is adapted to receive multiplexed addresses. The DRAM contains clock receiver circuitry for receiving an external clock signal. It further contains a programmable access-time register for storing a value which is representative of a first number of clock cycles of the external clock signal to transpire after which the DRAM responds to a write request received synchronously with respect to the external clock signal. The programmable access-time register is accessible to the external bus through the connection means. In order to set the value in the programmable access-time register, data is transmitted to the programmable access-time register over the external bus. The DRAM contains further a plurality of input receivers to receive write data from the external bus in response to the write request. The input receivers input the write data from the external bus after the first number of clock cycles transpire so that the write request and the corresponding receipt of write data are separated by the first number of clock cycles as selected by the value stored in the programmable access-time register.

    摘要翻译： 本发明涉及具有至少一个存储器阵列的动态随机存取存储器（DRAM）半导体器件，其包括以行和列排列的多个存储器单元。 DRAM包含适于将DRAM连接到作为半导体总线架构的一部分的外部总线的连接装置。 半导体总线架构包括与外部总线并联连接的多个半导体器件。 外部总线包括用于承载DRAM所需的基本上所有地址，数据和控制信息的多条总线，用于与连接到外部总线的基本上每个其他半导体器件进行通信。 连接装置适于接收复用的地址。 DRAM包含用于接收外部时钟信号的时钟接收器电路。 它还包含可编程存取时间寄存器，用于存储表示外部时钟信号的第一数量的时钟周期数值的值，之后DRAM响应于相对于外部时钟信号同步接收的写入请求。 可编程访问时间寄存器可通过连接方式访问外部总线。 为了设置可编程访问时间寄存器中的值，数据通过外部总线传输到可编程访问时间寄存器。 DRAM还包括多个输入接收器，以响应写入请求从外部总线接收写入数据。 输入接收器在第一数量的时钟周期之后输入来自外部总线的写入数据，使得写入请求和写入数据的对应接收被存储在可编程访问中的值所选择的第一数量的时钟周期分隔开 时间注册

    PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS
    6.
    发明授权
    PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS 失效
    与此同时，分组化，模块间-BASED HIGH-SPEED CONTROL AND BUS

    公开(公告)号：EP0907921B1

    公开(公告)日：2002-04-10

    申请号：EP97933270.7

    申请日：1997-06-27

    申请人： INTERDIGITAL TECHNOLOGY CORPORATION

    发明人： REGIS, Robert, T.

    IPC分类号： G06F13/374

    CPC分类号： H04B1/7075 ,  G06F13/374 ,  G06F13/376 ,  H04B1/70753 ,  H04B1/70755 ,  H04B1/70758 ,  H04B1/708 ,  H04B2201/70702

    摘要： A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the commzunication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the receiving module on the arbitration line and monitoring the arbitration line for collisions.

    A process for controlling access to a bus by several systems, for example for application in the domotic field, and associated interface devices
    9.
    发明公开
    A process for controlling access to a bus by several systems, for example for application in the domotic field, and associated interface devices 失效
    一种用于管理访问多个系统的总线，例如用于在家庭网络区域中使用的方法，以及接口装置，用于

    公开(公告)号：EP0689145A1

    公开(公告)日：1995-12-27

    申请号：EP95109682.5

    申请日：1995-06-22

    申请人： TEKNOX S.r.l.

    发明人： Bosio, Pier Giorgio ,  Gioannini, Luca

    IPC分类号： G06F13/376

    CPC分类号： G06F13/376 ,  G08B25/007 ,  G08B25/04 ,  G08B25/08

    摘要： In order to control access of several systems (S₁₀, S₁₁, ...; S₂₀, S₂₁, ...; S₃₀, S₃₁, ...) each operating according to its own specific mode, such as protocol, speed of transmission etc. to a common bus (B) there is provided a time division of access to the bus between the various systems. At the end of its transmission cycle the system which controls the bus (B) at the time generates an event constituting a synchronisation base for all the devices present on line. These then contribute to the formation of a successive conflict byte which leads to the identification of the system destined to gain control of the bus (B).

    摘要翻译： 为了控制若干系统的访问（S10，S11，...，S20，S21，...，S30，S31，...），每个操作gemäß到它自己的特定模式，颜色：如协议，传输速度等。 至公共总线（B），提供接入的时分到总线上的各个系统之间。 在其发送周期控制在时刻恢复构成用于所有存在于线中的装置的同步基事件的发生率的总线（B）的系统的端部。 然后，这些有助于连续冲突字节这导致注定要获得总线（B）的控制系统的识别的形成。