公开(公告)号：EP3364304A1

公开(公告)日：2018-08-22

申请号：EP18165222.3

申请日：2011-09-30

申请人： INTEL Corporation

发明人： NALE, Bill ,  RAMANUJAN, Raj K. ,  SWAMINATHAN, Muthukumar P. ,  THOMAS, Tessil ,  POLEPEDDI, Taarinya

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F11/10 ,  G06F13/14 ,  G06F13/16 ,  G06F9/46 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0811

CPC分类号： G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：EP3345101A1

公开(公告)日：2018-07-11

申请号：EP16741444.0

申请日：2016-06-30

申请人： Oracle International Corporation

发明人： KRISHNAPPA, Chinmayi ,  MARWAH, Vineet ,  GANESH, Amit

IPC分类号： G06F17/30

CPC分类号： G06F12/12 ,  G06F12/0802 ,  G06F17/3048 ,  G06F17/30569 ,  H03M7/30

摘要： Techniques are provided for maintaining data persistently in one format, but making that data available to a database server in more than one format. For example, one of the formats in which the data is made available for query processing is based on the on-disk format, while another of the formats in which the data is made available for query processing is independent of the on-disk format. Data that is in the format that is independent of the disk format may be maintained exclusively in volatile memory to reduce the overhead associated with keeping the data in sync with the on-disk format copies of the data. Selection of data to be maintained in the volatile memory may be based on various factors. Once selected the data may also be compressed to save space in the volatile memory. The compression level may depend on one or more factors that are evaluated for the selected data. The factors for the selection and compression level of data may be periodically evaluated, and based on the evaluation, the selected data may be removed from the volatile memory or its compression level changed accordingly.

公开(公告)号：EP3333715A1

公开(公告)日：2018-06-13

申请号：EP18152715.1

申请日：2001-08-08

申请人： Aware, Inc.

发明人： Gut, Ron Abraham ,  Tzannes, Alexis Paul ,  Reiter, Edmund Campion

IPC分类号： G06F12/08 ,  G06F17/30 ,  G06T1/60 ,  G06F12/0802 ,  G06F12/0875

CPC分类号： G06T1/60 ,  G06F12/0802 ,  G06F12/0875 ,  G06F16/10 ,  G06F2212/455

摘要： Methods and apparatus for constructing objects within a cache system thereby allowing the cache system to respond to requested objects that are not initially available within the cache system. One embodiment of the invention caches image files, where the images are divided into components and stored in a format that allows identification and access to the components. The cache system determines that an object, such as an image file, is missing from the cache memory, locates sufficient components from the cache memory and/or external storage, and constructs the object from the located components.

公开(公告)号：EP3242213A1

公开(公告)日：2017-11-08

申请号：EP17171776.2

申请日：2012-05-09

申请人： Intel Corporation

发明人： MACPHERSON, Mike B.

IPC分类号： G06F12/10 ,  G06F9/455

CPC分类号： G06F12/0802 ,  G06F9/06 ,  G06F9/30 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45554 ,  G06F9/45558 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/656 ,  G06F2212/657

摘要： Embodiments of techniques and systems for execution of code with multiple page tables are described. In embodiments, a heterogenous system utilizing multiple processors may use multiple page tables to selectively execute appropriate ones of different versions of executable code. The system may be configured to support use of function pointers to virtual memory addresses. In embodiments, a virtual memory address may be mapped, such as during a code fetch, in embodiments, when a processor seeks to perform a code fetch using the function pointer, a page table associated with the processor may be used to translate the virtual memory address to a physical memory address where code executable by the processor may be found. Usage of multiple page tables may allow the system to support function pointers while utilizing only one virtual memory address for each function that is pointed to. Other embodiments may be described and claimed.

公开(公告)号：EP3238117A1

公开(公告)日：2017-11-01

申请号：EP15872220.7

申请日：2015-12-16

申请人： Ricoh Company, Ltd.

发明人： NAGATA, Tadashi

IPC分类号： G06F21/45 ,  H04L29/06 ,  H04N1/00 ,  G06F3/00 ,  G06F11/00 ,  G06F21/57 ,  G06F21/31 ,  G06F21/60

CPC分类号： H04N1/4413 ,  G06F3/00 ,  G06F9/451 ,  G06F12/0802 ,  G06F21/31 ,  G06F21/575 ,  G06F21/608 ,  G06F2212/455 ,  G06F2212/60 ,  G06F2221/2145 ,  H04L63/0892 ,  H04N1/00 ,  H04N1/00244 ,  H04N1/4433 ,  H04N2201/0094

摘要： An information processing system includes a first storage that stores user information about one or more users of the information processing system; a second storage; a first determining unit that determines, depending on whether a program sets the second storage to store predetermined user information from the user information stored in the first storage, the predetermined user information being used in the program, whether to store the predetermined user information in the second storage; and a user information process unit that obtains the predetermined user information from the user information and stores the predetermined user information in the second storage if the first determining unit determines that the predetermined user information is to be stored in the second storage.

摘要翻译： 信息处理系统包括：第一存储器，存储关于信息处理系统的一个或多个用户的用户信息; 第二存储器; 第一确定单元，其根据程序是否设置第二存储器来存储来自存储在第一存储器中的用户信息的预定用户信息，在程序中使用预定用户信息，确定是否将预定用户信息存储在 第二存储; 以及用户信息处理单元，如果第一确定单元确定预定用户信息将被存储在第二存储装置中，则用户信息处理单元从用户信息中获得预定用户信息，并将预定用户信息存储在第二存储装置中。

公开(公告)号：EP3179374A4

公开(公告)日：2017-08-16

申请号：EP14888936

申请日：2014-10-23

申请人： ZTE CORP

发明人： WANG SHILONG

IPC分类号： G06F12/08 ,  G06F12/0802 ,  G06F12/14

CPC分类号： G06F12/1458 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1052

摘要： A method for checking validity of memory access is provided. In the method, a cache is established and initialization is performed; a total cache position index is calculated according to a size and address of a memory block to be checked; when a program performs memory access, a graded cache unit is addressed according to the total cache position index, and it is determined whether the address information of the memory block is able to be read from the graded cache unit; when the address information of the memory block is able to be read from the graded cache unit, it is determined, according to a range of the current memory access, whether an instrumentation-based memory checking tool is needed for checking the validity of the current memory access; when the address information of the memory block is not able to be read from the graded cache unit, the validity of the current memory access is checked by an instrumentation-based memory checking tool, and the address information of the memory block is filled into the graded cache unit when the current memory access is determined to be valid. A device used for realizing the above method is also provided. The technical solution can effectively improve the efficiency of checking the validity of memory access and improve software performance.

摘要翻译： 提供了用于检查存储器访问的有效性的方法。 在该方法中，建立缓存并执行初始化; 根据待检查的内存块的大小和地址计算总缓存位置索引; 当程序执行内存访问时，根据总高速缓存位置索引寻址分级高速缓存单元，并确定是否能够从分级高速缓存单元读取内存块的地址信息; 当能够从分级高速缓存单元中读取存储块的地址信息时，根据当前存储器访问的范围确定是否需要基于仪器的存储器检查工具来检查当前的有效性 内存访问; 当存储块的地址信息不能从分级高速缓存单元读取时，通过基于仪器的存储器检查工具来检查当前存储器访问的有效性，并且将存储器块的地址信息填入 当当前存储器访问被确定为有效时，分级高速缓存单元。 还提供了用于实现上述方法的设备。 该技术方案能够有效提高内存访问有效性检查的效率，提高软件性能。

公开(公告)号：EP2883147B1

公开(公告)日：2017-06-28

申请号：EP13827907.0

申请日：2013-08-08

申请人： NetApp, Inc.

发明人： COATNEY, Susan ,  BOLT, Thomas B. ,  LAMBERT, Laurent ,  RAMASUBRAMANIAM, Vaiapuri ,  PATEL, Chaitanya ,  REDDY, Sreelatha ,  KEREMANE, Hrishikesh ,  KADAYAM, Harihara

IPC分类号： G06F12/08 ,  G06F11/20

CPC分类号： G06F11/2023 ,  G06F11/20 ,  G06F11/2058 ,  G06F11/2092 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0866 ,  G06F2212/286

公开(公告)号：EP3182324A1

公开(公告)日：2017-06-21

申请号：EP16204801.1

申请日：2016-12-16

申请人： Fluke Corporation

发明人： HITTEL, John Paul ,  WOOTON, Clinton J.

IPC分类号： G06F21/64 ,  H04L29/06

CPC分类号： H04L43/50 ,  G06F12/0802 ,  G06F21/64 ,  G06F2212/154 ,  G06F2212/60 ,  G08C2201/93 ,  H04L9/14 ,  H04L9/30 ,  H04L63/0428 ,  H04L63/0442 ,  H04L63/06 ,  H04L2209/80 ,  H04Q2209/25 ,  H04Q2209/40 ,  H04Q2209/43 ,  H04Q2209/50 ,  H04Q2209/86 ,  H04W12/04

摘要： A system for providing data communication is provided. The system includes at least one computer test tool configured to perform one or more diagnostic tests on a computer network. The system further includes at least one communication device configured to couple to the at least one computer test tool to receive and cache test data from the at least one computer test tool and to wirelessly couple to a communication network. In addition, the system includes a cloud-based server configured to couple to the communication network so as to receive test data transmitted from the at least one communication device wherein the test data is encrypted in the at least one computer test tool and decrypted in the cloud-based server.

摘要翻译： 本发明提供一种用于提供数据通信系统。 该系统包括被配置为在计算机网络上执行一个或多个诊断测试的至少一个计算机测试工具。 该系统包括配置为耦合到所述至少一台计算机的测试工具的至少一个另外的通信设备接收和处理来自所述至少一台计算机的测试工具的高速缓存测试数据和以无线方式耦合到通信网络。 此外，该系统包括配置成耦合到所述通信网络的基于云的服务器，以接收测试数据的反式从所述至少一个通信设备worin测试数据在至少一个计算机测试工具加密，并在解密mitted 基于云计算的服务器。

公开(公告)号：EP3179374A1

公开(公告)日：2017-06-14

申请号：EP14888936.3

申请日：2014-10-23

申请人： ZTE Corporation

发明人： WANG, Shilong

IPC分类号： G06F12/08

CPC分类号： G06F12/1458 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1052

摘要： A method for checking validity of memory access is provided. In the method, a cache is established and initialization is performed; a total cache position index is calculated according to a size and address of a memory block to be checked; when a program performs memory access, a graded cache unit is addressed according to the total cache position index, and it is determined whether the address information of the memory block is able to be read from the graded cache unit; when the address information of the memory block is able to be read from the graded cache unit, it is determined, according to a range of the current memory access, whether an instrumentation-based memory checking tool is needed for checking the validity of the current memory access; when the address information of the memory block is not able to be read from the graded cache unit, the validity of the current memory access is checked by an instrumentation-based memory checking tool, and the address information of the memory block is filled into the graded cache unit when the current memory access is determined to be valid. A device used for realizing the above method is also provided. The technical solution can effectively improve the efficiency of checking the validity of memory access and improve software performance.

摘要翻译： 提供了用于检查存储器访问的有效性的方法。 在该方法中，建立缓存并执行初始化; 根据待检查的内存块的大小和地址计算总缓存位置索引; 当程序执行内存访问时，根据总高速缓存位置索引寻址分级高速缓存单元，并确定是否能够从分级高速缓存单元读取内存块的地址信息; 当能够从分级高速缓存单元中读取存储块的地址信息时，根据当前存储器访问的范围确定是否需要基于仪器的存储器检查工具来检查当前的有效性 内存访问; 当存储块的地址信息不能从分级高速缓存单元读取时，通过基于仪器的存储器检查工具来检查当前存储器访问的有效性，并且将存储器块的地址信息填入 当当前存储器访问被确定为有效时，分级高速缓存单元。 还提供了用于实现上述方法的设备。 该技术方案能够有效提高内存访问有效性检查的效率，提高软件性能。

公开(公告)号：EP3178005A1

公开(公告)日：2017-06-14

申请号：EP15742447.4

申请日：2015-07-09

申请人： Qualcomm Incorporated

发明人： TURNER, Andrew Edmund ,  PATSILARAS, George ,  RYCHLIK, Bohuslav

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

摘要： Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

摘要翻译： 用于压缩高速缓存的高速缓存行内的数据的方法，设备和非瞬态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基地址获得基础偏移量，以及通过用所获得的基础偏移量偏移基础地址来计算偏移地址，其中计算出的偏移地址与第二数据相关联 分割。 在一些方面中，该方法可以包括基于基地址识别第一数据段的奇偶校验值，并且通过使用识别的数据大小和识别的奇偶校验值在存储的表上执行查找来获得基准偏移量。