公开(公告)号：EP2761464B1

公开(公告)日：2018-10-24

申请号：EP11873012.6

申请日：2011-09-30

申请人： Intel Corporation

发明人： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  HINTON, Glenn, J.

IPC分类号： G11C13/00 ,  G06F12/0893

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

公开(公告)号：EP3385901A1

公开(公告)日：2018-10-10

申请号：EP18160825.8

申请日：2018-03-08

申请人： INTEL Corporation

发明人： NURVITADHI, Eriko ,  VEMBU, Balaji ,  LIN, Tsung-Han ,  SINHA, Kamal ,  BARIK, Rajkishore ,  GALOPPO VON BORRIES, Nicolas C.

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G06F9/4881 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F17/16 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/621 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/005 ,  G06T2200/28

摘要： An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

公开(公告)号：EP3382561A1

公开(公告)日：2018-10-03

申请号：EP18164922.9

申请日：2018-03-29

申请人： Pavilion Data Systems, Inc.

发明人： DANTKALE, Suhas ,  SATISH, Venkeepuram ,  GOVINDASAMY, Raghuraman

IPC分类号： G06F12/0868 ,  G06F12/02

CPC分类号： G06F11/1435 ,  G06F11/1451 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/1063 ,  G06F12/128 ,  G06F2201/84 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/285 ,  G06F2212/312 ,  G06F2212/621 ,  G06F2212/681 ,  G06F2212/69 ,  G06F2212/7203

摘要： A storage server includes an IO controller, a management controller and physical drives. The IO controller generates multiple metadata updates and writes a cache entry that includes the multiple metadata updates to a first cache in memory of the management controller. The IO controller additionally writes a copy of the cache entry to a second cache in a memory of the IO controller and increments a commit pointer in the first and second caches to indicate that the metadata updates are committed.

公开(公告)号：EP3380943A1

公开(公告)日：2018-10-03

申请号：EP16869033.7

申请日：2016-09-28

申请人： Intel Corporation

发明人： SASANKA, Ruchira

IPC分类号： G06F12/0811

CPC分类号： G06F12/0875 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/1045 ,  G06F2212/1021 ,  G06F2212/621

摘要： In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

公开(公告)号：EP3353660A1

公开(公告)日：2018-08-01

申请号：EP16770144.0

申请日：2016-09-09

申请人： Qualcomm Incorporated

发明人： LE, Hien, Minh ,  TRUONG, Thuong, Quang ,  XU, Kun ,  SUBRAMANIAM GANASAN, Jaya, Prakash ,  RAMIREZ, Cesar, Aaron

IPC分类号： G06F12/0815 ,  G06F9/52 ,  G06F12/0831

CPC分类号： G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

摘要： Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

公开(公告)号：EP3340011A1

公开(公告)日：2018-06-27

申请号：EP17184172.9

申请日：2017-08-01

申请人： Samsung Electronics Co., Ltd.

发明人： MOON, Dong-uk

IPC分类号： G06F1/32

CPC分类号： G06F5/14 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0831 ,  G06F12/0875 ,  G06F2205/126 ,  G06F2212/621 ,  Y02D10/128 ,  Y02D10/152

摘要： An electronic device according to some example embodiments includes a clock management circuit (210) configured to control a clock signal (CLK) and a processor circuit (220) directly connected to the clock management circuit (210) and configured to provide a clock control request for the clock signal (CLK) to the clock management circuit (210) according to an operation status of the processor circuit (220).

公开(公告)号：EP3291097A3

公开(公告)日：2018-05-30

申请号：EP17185832.7

申请日：2017-08-11

申请人： Google LLC

发明人： Coburn, Joel Dylan ,  Borchers, Albert ,  Johnson, Christopher Lyle ,  Sprinkle, Robert S.

IPC分类号： G06F12/0802 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/0868 ,  G06F12/0831

CPC分类号： G06F3/0685 ,  G06F3/0619 ,  G06F3/065 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0868 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

摘要： Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

公开(公告)号：EP3317764A1

公开(公告)日：2018-05-09

申请号：EP16745905.6

申请日：2016-06-30

申请人： Veritas Technologies LLC

发明人： DALAL, Chirag ,  BHARADWAJ, Vaijayanti

IPC分类号： G06F9/455 ,  G06F12/08

CPC分类号： G06F9/45558 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0875 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/621

摘要： Various systems, methods, and processes for accelerating data access in application and testing environments are disclosed. A production dataset is received from a storage system, and cached in a consolidated cache. The consolidated cache is implemented by an accelerator virtual machine. A file system client intercepts a request for the production dataset from one or more application virtual machines, and transmits the request to the accelerator virtual machine. The accelerator virtual machine serves the production dataset to the one or more application virtual machines from the consolidated cache.

公开(公告)号：EP3306479A1

公开(公告)日：2018-04-11

申请号：EP16192581.3

申请日：2016-10-06

申请人： Stichting IMEC Nederland ,  IMEC VZW

发明人： CATTHOOR, Francky ,  SETOAIN RODRIGO, Javier ,  GOMEZ, Jose Ignacio ,  PAPASTERGIOU, Thomas ,  TENLLADO, Christian ,  XYDIS, Sotiris ,  BALOUKAS, Christos ,  DAS, Anup Kumar ,  HARTMANN, Matthias ,  SOUDRIS, Dimitrios

IPC分类号： G06F12/0897 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/0864 ,  G06F12/02 ,  G06F9/50

CPC分类号： G06F12/1054 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/122 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/621 ,  G06F2212/652 ,  Y02D10/13

摘要： The present invention relates to a memory hierarchy for a system-in-package. The memory hierarchy is directly connectable to a processor (10) via a memory management unit arranged for translating a virtual address sent by said processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster (21) having one or more banks of scratchpad memory. The memory structure comprises a first data access controller (31) arranged for managing one or more of said banks of scratchpad memory of at least one of said clusters of at least said L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking, for each received physical address, if said physical address is present in said one or more banks of said at least one cluster of at least said L1 memory array and, if so, as a part of said managing, for forwarding a data request to one or more banks of scratchpad memory where said physical address is required, and if not, for forwarding said physical address to a cache controller (40) steering said data cache memory.

摘要翻译： 本发明涉及用于系统级封装的存储器层次结构。 存储器层级经由存储器管理单元可直接连接到处理器（10），所述存储器管理单元被布置用于将由所述处理器发送的虚拟地址转换为物理地址。 存储器层次结构具有数据高速缓冲存储器和具有至少一个L1存储器阵列的存储器结构，所述L1存储器阵列包括具有一个或多个暂存器存储器组的至少一个簇（21）。 所述存储器结构包括第一数据存取控制器（31），所述第一数据存取控制器（31）被安排用于管理至少所述L1存储器阵列的所述群集中的至少一个的所述暂存器存储器的所述存储体中的一者或一者以上，所述数据端口包括用于接收 并且被安排用于针对每个接收到的物理地址检查所述物理地址是否存在于所述至少一个L1存储器阵列的所述至少一个簇的所述一个或多个存储体中，并且如果存在，作为所述管理的一部分， 向需要所述物理地址的暂存器存储器的一个或多个存储体提供数据请求，如果不是，则向所述物理地址转发给高速缓存控制器（40）以转向所述数据高速缓存存储器。

公开(公告)号：EP2992436A4

公开(公告)日：2018-04-04

申请号：EP13883783

申请日：2013-04-30

申请人： HEWLETT PACKARD ENTPR DEVELOPMENT LP

发明人： BARRON DWIGHT L ,  FARABOSCHI PAOLO ,  JOUPPI NORMAN PAUL ,  KRAUSE MICHAEL R ,  LI SHENG

IPC分类号： G06F13/14 ,  G06F13/38

CPC分类号： G06F12/0813 ,  G06F12/0815 ,  G06F12/0824 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4234 ,  G06F15/167 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/621

摘要： According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.