公开(公告)号：EP3173931B1

公开(公告)日：2018-08-29

申请号：EP14901239.5

申请日：2014-09-01

申请人： Huawei Technologies Co., Ltd.

发明人： ZHU, Guanyu ,  XU, Jun ,  YU, Qun

IPC分类号： G06F12/00 ,  G06F17/30 ,  G06F3/06 ,  G06F12/109 ,  G06F12/1009

CPC分类号： G06F12/1009 ,  G06F3/0643 ,  G06F12/00 ,  G06F12/109 ,  G06F17/30091 ,  G06F17/30123 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/656 ,  G06F2212/657

摘要： A file access method and apparatus, and a storage system are provided. The method includes: receiving a file access request from a process, where the file access request includes a file identifier; accessing a first physical address space according to a preset first virtual address space and a preset first mapping relationship between the first virtual address space and the first physical address space, where the first physical address space stores a file system; obtaining an index node of a target file from the first physical address space according to the file identifier of the target file; obtaining a file page table of the target file according to file page table information, included in the index node, of the target file, where the file page table records a second physical address space in the first physical address space, a data page of the target file is stored in the second physical address space; and accessing the target file according to the second physical address space. Therefore, software running overheads can be reduced effectively during file access, and a file access speed can be increased.

公开(公告)号：EP3314523A1

公开(公告)日：2018-05-02

申请号：EP16814980.5

申请日：2016-05-26

申请人： Intel Corporation

发明人： ZMUDZINSKI, Krystof C. ,  SHANBHOGUE, Vedvyas

IPC分类号： G06F21/79 ,  G06F21/60 ,  G06F12/14 ,  G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/1052 ,  G06F2212/305 ,  G06F2212/651 ,  G06F2212/684

摘要： A processor of an aspect includes at least one translation lookaside buffer (TLB) and a memory management unit (MMU). Each TLB is to store translations of logical addresses to corresponding physical addresses. The MMU, in response to a miss in the at least one TLB for a translation of a first logical address to a corresponding physical address, is to check for a multi-page protected container page versus regular page (P/R) check hint. If the multi-page P/R check hint is found, then the MMU is to check a P/R indication. If the multi-page P/R check hint is not found, then the MMU does not check the P/R indication. Other processors, methods, and systems are also disclosed.

公开(公告)号：EP2510444B1

公开(公告)日：2015-07-08

申请号：EP11703260.7

申请日：2011-02-08

申请人： ARM Limited

发明人： GRISENTHWAITE, Richard, Roy

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/1009 ,  G06F2212/651

公开(公告)号：EP1846829B1

公开(公告)日：2013-07-03

申请号：EP05819727.8

申请日：2005-12-14

申请人： Sony Computer Entertainment Incorporated

发明人： YAMAZAKI, T., c/o SONY COMPUTER ENTERTAINMENT INC.

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/10 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/651 ,  G06F2212/652

摘要： Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; using the second portion of the first intermediate address to produce a second intermediate address; and using at least a portion of the second intermediate address as a pointer directly to one of the referenced entries in the page table to obtain an at least partially translated physical address into the memory for the external address.

公开(公告)号：EP1393184B1

公开(公告)日：2012-10-17

申请号：EP02740602.4

申请日：2002-05-14

申请人： Infineon Technologies AG

发明人： GAMMEL, Berndt ,  SEDLAK, Holger ,  MAY, Christian ,  LEDWA, Ralph

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/1009 ,  G06F2212/651 ,  G06F2212/681

公开(公告)号：EP3311268A1

公开(公告)日：2018-04-25

申请号：EP16720486.6

申请日：2016-04-26

申请人： Arm Ltd

发明人： PARKER, Jason ,  GRISENTHWAITE, Richard Roy ,  ROSE, Andrew Christopher ,  EVANS, Matthew Lucien

IPC分类号： G06F9/455 ,  G06F12/14 ,  G06F21/53

CPC分类号： G06F12/1458 ,  G06F9/455 ,  G06F9/50 ,  G06F12/0646 ,  G06F12/1036 ,  G06F12/1408 ,  G06F21/805 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/651

摘要： A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

公开(公告)号：EP3183682A2

公开(公告)日：2017-06-28

申请号：EP15879117.8

申请日：2015-08-11

申请人： Bitdefender IPR Management Ltd.

发明人： LUKACS, Sandor ,  LUTAS, Andrei-Vlad

IPC分类号： G06F21/53 ,  G06F21/55 ,  G06F21/56 ,  G06F9/455 ,  G06F12/08 ,  G06F12/14 ,  G06F12/109 ,  G06F12/1027 ,  H04L29/06

CPC分类号： G06F21/554 ,  G06F9/45558 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/1475 ,  G06F12/1483 ,  G06F21/53 ,  G06F21/56 ,  G06F2009/45587 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2221/033 ,  H04L63/145

摘要： Described systems and methods enable a host system to efficiently perform computer security activities, when operating in a hardware virtualization configuration. A processor is configured to generate a VM suspend event (e.g., a VM exit or a virtualization exception) when a guest instruction executing within a guest VM performs a memory access violation. In some embodiments, the processor is further configured to delay generating the VM suspend event until the execution stage of the pipeline for the guest instruction is complete, and to save results of the execution stage to a specific location (e.g. a specific processor register readable by security software) before generating the event.

摘要翻译： 当在硬件虚拟化配置中操作时，所描述的系统和方法使得主机系统能够有效地执行计算机安全活动。 处理器被配置成当在访客VM内执行的访客指令执行存储器访问冲突时产生VM中止事件（例如，VM退出或虚拟化异常）。 在一些实施例中，处理器还被配置为延迟产生VM暂停事件，直到用于访客指令的流水线的执行阶段完成，并且将执行阶段的结果保存到特定位置（例如，特定处理器寄存器 安全软件）在生成事件之前。

公开(公告)号：EP2718823A1

公开(公告)日：2014-04-16

申请号：EP12729774.5

申请日：2012-06-08

申请人： Apple Inc.

发明人： PALEY, Alexander ,  SADE, Asif

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F2212/651 ,  G06F2212/7201 ,  G06F2212/7205

摘要： A method for operating a memory includes receiving memory access commands associated with respective target logical addresses, for execution in a memory. The target logical addresses are translated into respective intermediate logical addresses, in accordance with a first mapping having a first granularity of a first data unit size. The intermediate logical addresses are translated into respective physical storage locations in the memory, in accordance with a second mapping having a second granularity of a second data unit size, larger than the first data unit size. The memory access commands are executed in the memory in accordance with the respective physical storage locations.

摘要翻译： 用于操作存储器的方法包括接收与各个目标逻辑地址相关联的存储器访问命令，以便在存储器中执行。 根据具有第一数据单元大小的第一粒度的第一映射，将目标逻辑地址转换为相应的中间逻辑地址。 根据具有大于第一数据单元大小的第二数据单元大小的第二粒度的第二映射，将中间逻辑地址转换为存储器中的相应物理存储位置。 存储器访问命令根据相应的物理存储位置在存储器中执行。

公开(公告)号：EP2350833A2

公开(公告)日：2011-08-03

申请号：EP09822390.2

申请日：2009-09-26

申请人： Microsoft Corporation

发明人： FOLTZ, Forrest, C. ,  CUTLER, David, N.

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F12/08

CPC分类号： G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

摘要： Page tables in the last level of a hierarchical page table system are scanned for candidate page tables. Candidate page tables are converted to large pages, having a page table entry in a level before the last level of the hierarchical page table system adjusted to be associated with the newly created large page. Upon receiving a notification that a large page is to be converted into a page table, a new page table is created. Each entry in the new page table is associated with a small segment of memory in the large page and an entry in a page table one level before the last level in a hierarchical page table system is adjusted to be associated with the new page table.

公开(公告)号：EP1846829A1

公开(公告)日：2007-10-24

申请号：EP05819727.8

申请日：2005-12-14

申请人： Sony Computer Entertainment Inc.

发明人： YAMAZAKI, T., c/o SONY COMPUTER ENTERTAINMENT INC.

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/10 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/651 ,  G06F2212/652

摘要： Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; using the second portion of the first intermediate address to produce a second intermediate address; and using at least a portion of the second intermediate address as a pointer directly to one of the referenced entries in the page table to obtain an at least partially translated physical address into the memory for the external address.