公开(公告)号：EP4439323A1

公开(公告)日：2024-10-02

申请号：EP23213816.4

申请日：2023-12-01

申请人： Intel Corporation

发明人： REGUPATHY, Rajaram ,  ROZIC, Reuven ,  BERCHANSKIY, Dmitriy ,  BAILUR, Nirmala ,  PANSE, Vrukesh V. ,  GOPAL, Saranya

IPC分类号： G06F13/42

CPC分类号： G06F13/4295 ,  G06F2213/004220130101 ,  G06F2213/006220130101

摘要： A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

公开(公告)号：EP4439320A1

公开(公告)日：2024-10-02

申请号：EP23216243.8

申请日：2023-12-13

申请人： INTEL Corporation

发明人： SUBRAMANIAN, Ravishankar ,  GOPALAKRISHNAN, Venkataramani ,  HAYAT, Yaniv ,  ROZIC, Reuven

IPC分类号： G06F13/40 ,  G06F13/42 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/70 ,  H04L47/83 ,  G06F1/3234

CPC分类号： G06F13/4282 ,  G06F2213/002620130101 ,  G06F2213/006220130101 ,  G06F2213/381220130101 ,  G06F13/4045 ,  H04L47/83 ,  H04L47/826 ,  H04L43/16 ,  G06F1/3253 ,  G06F13/4081 ,  H04L43/0894

摘要： Embodiments herein relate to reducing the power consumption of a serial link (103) such as Peripheral Component Interconnect Express (PCIe) link (103). The link (103) may extend between a System-On-A-Chip, SoC, (101) and a Universal Serial Bus, USB4, host (102) in a computing device (100). The USB4 host includes a PCIe switch (150) which connects lanes of the link (103) to adapters (171 - 177) in a USB4 router (170), such as a USB3 adapter (171, 172), a PCIe adapter (173, 174), a host interface adapter (175) and a DisplayPort adapter (176, 177). The available bandwidth of the link (103) can be adjusted based on a measured data rate. For example, the data rate can be compared to one or more thresholds. In one approach, the data rate is based on downstream transmissions, from the SoC (101) to the USB4 host (102). A transmitter clock rate can be adjusted to adjust the bandwidth and reduce power consumption.