公开(公告)号：EP4343562A1

公开(公告)日：2024-03-27

申请号：EP23183037.3

申请日：2023-07-03

申请人： Intel Corporation

发明人： BAILUR, Nirmala ,  CHAUHAN, Shailendra Singh ,  A/L SASIDARAN, Dhinesh ,  CHEE, Pik Shen ,  GOPALAKRISHNAN, Venkataramani ,  GUNNAM, Mahesh ,  HUANG, Yi Jen ,  JANGILI GANGA, Siva Prasad ,  KALISWAMY, Karthi ,  KONG, Jackson Chung Peng ,  KOTAKONDA, Venkataramana ,  LIM, Kie Woon ,  MEDEPALLI, Uma ,  RAVALI, Pampala ,  SATHEESAKURUP, Sreejith ,  SUNDER RAMAN, Charuhasini ,  SAVARIEGO, Tomer ,  SHAH, Kunal ,  TAN, Chuen Ming ,  VANKUNAVATH, Ramesh ,  ZAMANI, M. Reza ,  BANU, W. Naznin ,  JEEVARATHINAM, Surendar ,  KODALI, Sindhusha ,  MAHAJAN, Rohit ,  SHARMA, Deepak ,  SHETTY, Madhura ,  VENKATARAUYAPPA, Manjunatha

IPC分类号： G06F13/38

摘要： Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.

公开(公告)号：EP4439320A1

公开(公告)日：2024-10-02

申请号：EP23216243.8

申请日：2023-12-13

申请人： INTEL Corporation

发明人： SUBRAMANIAN, Ravishankar ,  GOPALAKRISHNAN, Venkataramani ,  HAYAT, Yaniv ,  ROZIC, Reuven

IPC分类号： G06F13/40 ,  G06F13/42 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/70 ,  H04L47/83 ,  G06F1/3234

CPC分类号： G06F13/4282 ,  G06F2213/002620130101 ,  G06F2213/006220130101 ,  G06F2213/381220130101 ,  G06F13/4045 ,  H04L47/83 ,  H04L47/826 ,  H04L43/16 ,  G06F1/3253 ,  G06F13/4081 ,  H04L43/0894

摘要： Embodiments herein relate to reducing the power consumption of a serial link (103) such as Peripheral Component Interconnect Express (PCIe) link (103). The link (103) may extend between a System-On-A-Chip, SoC, (101) and a Universal Serial Bus, USB4, host (102) in a computing device (100). The USB4 host includes a PCIe switch (150) which connects lanes of the link (103) to adapters (171 - 177) in a USB4 router (170), such as a USB3 adapter (171, 172), a PCIe adapter (173, 174), a host interface adapter (175) and a DisplayPort adapter (176, 177). The available bandwidth of the link (103) can be adjusted based on a measured data rate. For example, the data rate can be compared to one or more thresholds. In one approach, the data rate is based on downstream transmissions, from the SoC (101) to the USB4 host (102). A transmitter clock rate can be adjusted to adjust the bandwidth and reduce power consumption.

公开(公告)号：EP4268050A1

公开(公告)日：2023-11-01

申请号：EP21911794.2

申请日：2021-09-20

申请人： INTEL Corporation

发明人： GOPALAKRISHNAN, Venkataramani ,  RAVISHANKAR, S. ,  HAYAT, Yaniv ,  HUANG, Yi Jen

IPC分类号： G06F1/3234 ,  G06F1/3293 ,  G06F1/3206