摘要:
Disclosed are a shift register unit, an operation method therefor and a shift register comprising the shift register unit. The shift register unit comprises: an input module configured to transmit a received input signal to a pull-up node; an output module configured to output a first control signal of a first control signal end to an output end when a pull-up signal at the pull-up node is at an effective pull-up level; and a coupling module, wherein the first end thereof is connected to a second control signal end, the second end thereof is connected to the pull-up node, and the coupling module is configured to control the pull-up signal at the pull-up node in a voltage coupling manner according to a second control signal of the second control signal end. By further pulling up the voltage at the pull-up node when an output end is reset, the speed of resetting the output end can be increased.
摘要:
The present invention provides an organic light emitting display device including a display panel, a data driver, and a scan driver. The display panel includes sub-pixels. The data driver supplies a data pixel to the sub-pixels. The scan driver supplies a scan signal for controlling a switching transistor of each sub-pixel, and a sensing signal for controlling a sensing transistor of each sub-pixel. The sensing transistor has a turn-on time for detecting whether a short has occurred between at least two electrodes of a switching transistor in response to a sensing signal.
摘要:
A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor, wherein a gate of the second transistor is directly connected to a third wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a fifth wiring, wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor, wherein a gate of the fifth transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor, wherein a gate of the sixth transistor is directly connected to the sixth wiring, wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor. wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor, wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and wherein a gate of the ninth transistor is directly connected to the seventh wiring.
摘要:
A pixel includes a pixel circuit and an organic light emitting diode. The pixel circuit has first, second, third, and fourth transistors. The first transistor controls an amount of current flowing from a first driving power supply coupled to a first node to a second driving power supply through the organic light emitting diode. The turns on when a scan signal is supplied to a first scan line. The third transistor turns on when a scan signal is supplied to a second scan line. The fourth transistor turns on when a scan signal is supplied to a third scan line. The first transistor is a p-type Low Temperature Poly-Silicon thin film transistor and the third transistor and the fourth transistor are n-type oxide semiconductor thin film transistors.
摘要:
A display panel comprising a light guide plate; a main light source configured to emit light from a first lateral surface of the light guide plate in a first direction; a sub-light source configured to emit light from a second lateral surface vertical to the first lateral surface of the light guide plate in a second direction perpendicular to the first direction; and a liquid crystal panel provided in a front surface of the light guide plate and configured to output image information.
摘要:
The image display apparatus is provided with a dot matrix of light emitting devices, driver circuitry, and switching circuitry. The dot matrix is a plurality of light emitting devices arranged in an m-line by n-column matrix, and one terminal of each light emitting device in each line is connected to a common source line. Driver circuitry controls light emitting devices active or inactive depending on an input illumination signal. In the active state, switching circuitry floats common source lines, and in the inactive state, discharges all common source lines to ground.
摘要:
A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor, wherein a gate of the second transistor is directly connected to a third wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a fifth wiring, wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor, wherein a gate of the fifth transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor, wherein a gate of the sixth transistor is directly connected to the sixth wiring, wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor. wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor, wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and wherein a gate of the ninth transistor is directly connected to the seventh wiring.
摘要:
A method of driving a display apparatus includes determining a duration of a blank interval between a first frame and a second frame, wherein the second frame is subsequent to the first frame, and modulating a common voltage during the blank interval when the duration is longer than a first reference time, wherein an average of the common voltage is fixed during the blank interval.
摘要:
A display apparatus which outputs a stereoscopic image and a control method thereof, the display apparatus includes: an image input part which receives left and right eye image frames; an image processor which generates a left eye image interpolation frame by using a gradation difference of areas between a previous right eye image frame of the left eye image frame and the left eye image frame and generates a right eye image interpolation frame by using a gradation difference of areas between a previous left eye image frame of the right eye image frame and the right eye image frame; a display which displays the left eye image interpolation frame, the left eye image frame, the right eye image interpolation frame, and the right eye image frame sequentially according to a preset order; and a controller which controls the image processor to generate the left and right eye image interpolation frames.