公开(公告)号：EP2757580A1

公开(公告)日：2014-07-23

申请号：EP13152160.1

申请日：2013-01-22

申请人： NXP B.V.

发明人： Boos, Priscilla ,  Van Dalen, Rob ,  Spaan, Erick

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/762

CPC分类号： H01L27/0623 ,  H01L21/76221 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7302

摘要： There is disclosed a method of manufacturing a high voltage, HV, device with a BCD process. The method comprises undertaking a Local Oxidation of Silicon, LOCOS, fabrication process to form a recessed insulating structure prior to undertaking a Bipolar CMOS DMOS, BCD, fabrication process to form a plurality of device layers on the recessed insulating structure.

摘要翻译： 公开了一种制造具有BCD工艺的高压HV装置的方法。 该方法包括进行硅局部氧化，LOCOS制造工艺，以在进行双极CMOS DMOS，BCD制造工艺之前形成凹陷绝缘结构，以在凹陷绝缘结构上形成多个器件层。

公开(公告)号：EP1049172B1

公开(公告)日：2007-04-11

申请号：EP00104155.7

申请日：2000-02-29

申请人： Oki Electric Industry Co., Ltd.

发明人： Hayashi, Hirokazu, c/o Oki Electric Ind. Co., Ltd. ,  Fukuda, Kouichi, c/o Oki Electric Ind. Co., Ltd. ,  Miura, Noriyuki, c/o Oki Electric Ind. Co., Ltd.

IPC分类号： H01L21/762 ,  H01L21/32 ,  H01L21/316 ,  H01L21/265 ,  H01L29/786 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/76264 ,  H01L21/32 ,  H01L21/76267 ,  H01L21/76281

公开(公告)号：EP1676311A1

公开(公告)日：2006-07-05

申请号：EP04793289.2

申请日：2004-10-25

申请人： SONY CORPORATION ,  The Regents of the University of California

发明人： KISHIMA, Koichiro ,  KOONATH, Prakash

IPC分类号： H01L21/762 ,  H01L21/266

CPC分类号： H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281

摘要： A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then stripping off the mask and the surface protection layer. A silicon dioxide layer (102) has a first top surface (102a) corresponding to an area where the mask has not existed and having a relatively long distance from the major surface (100a), and a second top surface (102b) corresponding to an area where the mask has existed and having a relatively short distance from the major surface (100a). As this major surface (100a) is polished by a predetermined quantity, a semiconductor substrate is provided in which only a part of a single-crystal silicon substrate is a SOI substrate.

公开(公告)号：EP0543361B1

公开(公告)日：2002-02-27

申请号：EP92119700.0

申请日：1992-11-19

申请人： CANON KABUSHIKI KAISHA

发明人： Miyawaki, Mamoru, c/o Canon Kabushiki Kaisha ,  Kawasumi, Yasushi, c/o Canon Kabushiki Kaisha ,  Inoue, Shunsuke, c/o Canon Kabushiki Kaisha ,  Akino, Yutaka, c/o Canon Kabushiki Kaisha ,  Koizumi, Toru, c/o Canon Kabushiki Kaisha ,  Kohchi, Tetsunobu, c/o Canon Kabushiki Kaisha

IPC分类号： H01L21/76 ,  H01L21/82 ,  H01L21/20 ,  G01N21/88

CPC分类号： H01L21/3226 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/76286 ,  H01L23/544 ,  H01L27/092 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0862787A1

公开(公告)日：1998-09-09

申请号：EP97930597.0

申请日：1997-06-26

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE

发明人： DELEONIBUS, Simon

IPC分类号： H01L21 ,  H01L29

CPC分类号： H01L21/76264 ,  H01L21/76281

摘要： The invention concerns a MOSFET transistor comprising a silicon layer portion (114), forming an active region (114a), arranged between a grid oxide layer (120) and a buried oxide layer (112), and laterally delimited by lateral insulating oxide tiles (116). The silicon layer portion has concave edges (122, 124) facing the lateral insulating oxide tiles. The invention is useful in the manufacture of integrated circuits with low electricity consumption.

公开(公告)号：EP0756319A3

公开(公告)日：1998-01-07

申请号：EP96111564.9

申请日：1996-07-18

申请人： MOTOROLA, INC.

发明人： Racanelli, Marco ,  Shin, Hyungcheol ,  Park, Heemyong

IPC分类号： H01L21/762 ,  H01L21/32

CPC分类号： H01L21/76264 ,  H01L21/32 ,  H01L21/76267 ,  H01L21/76275 ,  H01L21/76281

摘要： A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

摘要翻译： 提供了一种用于在一个SOI衬底（11）上的隔离结构（22）的形成方法。 的蚀刻剂的阻挡层（16）的三层叠层，应力缓和层（17），和氧化掩模层（18）上形成SOI衬底（11）上。 三层叠层构图并蚀刻以暴露蚀刻阻挡层（16）的部分。 腐蚀剂阻挡层（16）的暴露部分下方的硅层（13）被氧化以形成隔离结构（22）。 隔离结构（22）包括一个鸟的头区域（21）具有小的侵蚀，这导致较高的边缘的阈值电压。 该方法需要最小过度氧化，并提供了在隔离结构（22）没有离开SOI衬底（11）是平面的。 最小的过氧化降低在氧化工艺形成位错的数量，并提高了源极到漏极的器件的漏。

公开(公告)号：EP0637838A3

公开(公告)日：1997-12-29

申请号：EP94305564

申请日：1994-07-27

申请人： AT & T CORP

发明人： BEITMAN BRUCE ALLAN

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  Y10S148/012 ,  Y10S148/05

公开(公告)号：EP0810652A2

公开(公告)日：1997-12-03

申请号：EP97111478.0

申请日：1993-01-27

申请人： CANON KABUSHIKI KAISHA

发明人： Inoue, Shunsuke ,  Miyawaki, Mamoru ,  Kohchi, Tetsunobu

IPC分类号： H01L21/8238 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/8238 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78684

摘要： A semiconductor device has an insulated gate transistor in which source and drain regions are provided in a single crystal semiconductor layer formed on an insulating layer with a channel region interposed between the source and drain regions. An insulating layers just below the source and drain regions are made thicker than an insulating layer just below the channel region.

公开(公告)号：EP0687002A3

公开(公告)日：1996-11-13

申请号：EP95108390.6

申请日：1995-05-31

申请人： KOMATSU ELECTRONIC METALS CO., LTD ,  NIPPON TELEGRAPH AND TELEPHONE CORPORATION ,  NTT ELECTRONICS TECHNOLOGY CORPORATION

发明人： Nakashima, Sadao, c/o Nippon Telegraph and Tel. ,  Izumi, Katsutoshi, c/o Nippon Telegraph and Tel. ,  Ohwada, Norihiko, c/o NTT Electronics Technology ,  Katayama, Tatsuhiko, c/o Komatsu Elect. Metals Co.

IPC分类号： H01L21/762 ,  H01L21/82 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/84 ,  Y10S438/981

摘要： A SIMOX substrate 1 is processed through high temperature oxidation treatment after forming a mask-pattern 3 to shield specified electrodes from oxidation in order to increase partly a thickness of a buried oxide layer 2 to form an area 4. Next, after an oxide film is removed from the surface of the substrate and LOCOS separation is practiced, MOSFET is produced by fabricating a source S and a drain D on the area 4 or the buried oxide layer 2. Since the buried oxide layer corresponding to electrodes parts influenced by disadvantages of parasitic capacitance are thickened, an operation speed of an inverter is not much decreased and since mean thickness of the buried oxide layer can be thinner, a decrease of a drain electric current by negative electrical resistance can be suppressed. Furthermore, since the thickness of the buried oxide layer can be controlled in response to each device, plural devices having different breakdown voltages are formed together on the same substrate.

公开(公告)号：EP0545585A3

公开(公告)日：1996-11-06

申请号：EP92310586.0

申请日：1992-11-19

申请人： AT&T Corp.

发明人： Lee, Kuo-Hua ,  Yu, Chen-Hau Douglas

IPC分类号： H01L21/32 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76264 ,  H01L21/76281

摘要： A method of semiconductor integrated circuit fabrication is disclosed. An amorphous silicon layer (e.g., 15) is deposited between an oxide layer (e.g., 13) and a nitride layer (e.g., 17) in an improved poly buffered LOCOS process. When the amorphous silicon (e.g., 15) is oxidized it provides a field oxide (e.g., 23) with a smoother upper surface.

摘要翻译： 公开了一种半导体集成电路制造方法。 在改进的多重缓冲LOCOS工艺中，非晶硅层（例如15）沉积在氧化物层（例如13）和氮化物层（例如17）之间。 当非晶硅（例如15）被氧化时，其提供具有更平滑的上表面的场氧化物（例如23）。