公开(公告)号：EP4415508A2

公开(公告)日：2024-08-14

申请号：EP24186129.3

申请日：2018-10-31

申请人： SOITEC

发明人： GHYSELEN, Bruno ,  BETHOUX, Jean-Marc

IPC分类号： H10N30/073

CPC分类号： H01L21/76254 ,  H01L21/76264 ,  H01L21/76283 ,  H10N30/073 ,  H10N30/072

摘要： The invention relates to a method for manufacturing a film (12) on a support (20) having a non-flat surface, characterised in that it comprises:
- the supply of a donor substrate (10) having a non-flat surface,
- the formation of an embrittlement zone (11) in the donor substrate (10) so as to delimit said film (12) to transfer,
- the formation of the support (20) by conformal deposition on the non-flat surface of the film (12) to transfer,
- the detachment of the donor substrate (10) along the embrittlement zone (11), so as to transfer said film (12) onto the support (20).

公开(公告)号：EP2823506B1

公开(公告)日：2018-01-10

申请号：EP13757434.9

申请日：2013-02-01

申请人： Silicon Storage Technology Inc.

发明人： TOREN, Willem-jan ,  LIU, Xian ,  METZGER-BRUECKL, Gerhard ,  DO, Nhan ,  WEGE, Stephan ,  MIRIDI, Nadia ,  SU, Chien-sheng ,  BERNARDI, Cecile ,  CUEVAS, Liz ,  GUYOT, Florence ,  CHEN, Yueh-hsin ,  OM'MANI, Henry ,  TADAYONI, Mandana

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

摘要： A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

公开(公告)号：EP3084806A4

公开(公告)日：2017-07-26

申请号：EP13899945

申请日：2013-12-18

申请人： INTEL CORP

发明人： JUN KIMIN ,  MORROW PATRICK

IPC分类号： H01L21/8258 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/8258 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/78

摘要： In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.

摘要翻译： 在一个实施例中，第二半导体层在第一半导体层上被转移（例如，使用层转移技术）。 第二层被图案化成所需的孔。 在井之间，第一层被暴露。 暴露的第一层外延生长到转移的第二层的水平以完成包括S1和S2两者的平面异质衬底。 可以使用非均质材料，使得例如由III-V或IV材料中的一种形成的P沟道器件与由III-V或IV材料中的一种形成的N沟道器件共面。 由于第二层被转移到第一层上，该实施例不需要晶格参数顺从性。 此外，没有（或很少）缓冲和/或异质外延。 这里描述了其他实施例。

公开(公告)号：EP3132468A1

公开(公告)日：2017-02-22

申请号：EP15780680.3

申请日：2015-04-13

申请人： Texas Instruments Incorporated

发明人： CAROTHERS, Daniel Nelson ,  DEBORD, Jeffrey R.

IPC分类号： H01L21/762

CPC分类号： H01L29/0653 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/7851

摘要： An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

摘要翻译： 可以通过在单晶硅基衬底的隔离凹槽中形成掩埋隔离层来形成集成电路。 掩埋隔离层处的衬底的暴露的侧表面被电介质侧壁覆盖。 通过掩埋隔离层形成晶种沟以暴露衬底。 通过晶种沟槽形成单晶硅基种子层，在掩埋隔离层的顶表面上方延伸。 形成接触种子层的硅基非晶层。 在非晶层上形成覆盖层。 辐射诱导的再结晶过程将非结晶层转化成与种子层对准的单晶层。 除去盖层并且使单晶层平坦化，在掩埋隔离层上留下隔离的半导体层。

公开(公告)号：EP2573807A1

公开(公告)日：2013-03-27

申请号：EP11290430.5

申请日：2011-09-23

申请人： Soitec

发明人： Bourdelle, Konstantin

IPC分类号： H01L21/762

CPC分类号： H01L21/76237 ,  H01L21/76283

摘要： The present invention relates to a semiconductor structure including a bulk semiconductor; a thin semiconductor layer; an insulating layer between the bulk semiconductor and the thin semiconductor layer; a trench; and a side wall doped region, on at least a region of the inner surface of the trench.

摘要翻译： 本发明涉及包括体半导体的半导体结构; 薄的半导体层; 体半导体和薄半导体层之间的绝缘层; 沟渠 和侧壁掺杂区域，在沟槽的内表面的至少一个区域上。

公开(公告)号：EP2416357A2

公开(公告)日：2012-02-08

申请号：EP10195217.4

申请日：2010-12-15

申请人： Intersil Americas Inc.

发明人： Gaul, Stephen J. ,  Church, Michael D. ,  Jerome, Rick Carlton

IPC分类号： H01L23/367

CPC分类号： H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L23/3735 ,  H01L25/065 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region.

摘要翻译： 一种电子系统，制造一个半导体结构的，和一个或多个半导体结构的方法游离缺失光盘。 例如，在制造半导体结构的方法是游离缺失盘，其包括上方形成的热传导层的半导体层，在隔离区域上的热传导层形成，并在隔离区域上形成的热传导区域。

公开(公告)号：EP2390907A1

公开(公告)日：2011-11-30

申请号：EP11003289.3

申请日：2011-04-19

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Bourdelle, Konstantin ,  Mazure, Carlos

IPC分类号： H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/76275 ,  H01L29/66181

摘要： The present invention relates to a method for the manufacture of a trench structure in a multilayer wafer comprising a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer, the method comprising the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate and performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench.

摘要翻译： 本发明涉及在多层晶片中制造沟槽结构的方法，该方法包括：衬底，衬底上的氧化物层和氧化物层上的半导体层，该方法包括以下步骤：通过半导体层形成沟槽 和氧化物层并延伸到衬底中并对形成的沟槽进行退火处理，使得在沟槽的内表面处，半导体层的一些材料至少在暴露在内部的氧化物层的一部分上流动 表面的沟槽。

公开(公告)号：EP2122677A4

公开(公告)日：2011-11-23

申请号：EP08729122

申请日：2008-02-06

申请人： FREESCALE SEMICONDUCTOR INC

发明人： HALL MARK D ,  ABELN GLENN C ,  GRANT JOHN M

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L27/11

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66757 ,  H01L29/78621

公开(公告)号：EP2161742A1

公开(公告)日：2010-03-10

申请号：EP08290827.8

申请日：2008-09-03

申请人： S.O.I.TEC Silicon on Insulator Technologies S.A. ,  Commissariat A L'Energie Atomique - CEA

发明人： Signamarcheix, Thomas ,  Allibert, Frederic ,  Deguet, Chrystel

IPC分类号： H01L21/762 ,  H01L29/786

CPC分类号： H01L29/16 ,  H01L21/318 ,  H01L21/76254 ,  H01L21/76283

摘要： The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment.

摘要翻译： 本发明涉及一种用于制造局部钝化的绝缘体上的锗衬底的方法，其中为了获得良好的电子迁移率，在局部位置提供氮化区域。 使用等离子体处理实现氮化。

公开(公告)号：EP2122677A1

公开(公告)日：2009-11-25

申请号：EP08729122.5

申请日：2008-02-06

申请人： Freescale Semiconductor, Inc.

发明人： HALL, Mark D. ,  ABELN, Glenn C. ,  GRANT, John M.

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66757 ,  H01L29/78621

摘要： A semiconductor device (10) is formed on a semiconductor layer (16). A gate dielectric layer (18) is formed over the semiconductor layer. A layer of gate material (20) is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure (20). Using the gate structure as a mask, an implant (24) into the semiconductor layer is performed. To form a first patterned gate structure (20) and a trench (42) in the semiconductor layer (16) surrounding a first portion (28) and a second portion (30) of the semiconductor layer and the gate, an etch through the gate structure (20) and the semiconductor layer (16) is performed. The trench (42) is filled with insulating material (46).