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公开(公告)号：EP0316952B1
公开(公告)日：1993-08-25
申请号：EP88119243.9
申请日：1988-11-18
IPC分类号： H03D1/22
CPC分类号： H03D1/2236 , H03D1/2209
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公开(公告)号：EP3226433A3
公开(公告)日：2017-10-25
申请号：EP17158554.0
申请日：2017-02-28
申请人： Intel IP Corporation
发明人： ZHU, Jie , FIEVET, Sebastien , KUTTAN, Sathish K.
IPC分类号： H04B5/00 , H04W4/00 , H03D1/00 , H03D1/02 , H03D1/22 , H04L25/06 , H03D3/00 , H03D3/06 , H03D3/18 , H04L27/06 , H03K9/02 , H04L27/233
CPC分类号： H04B5/02 , H03D1/2209 , H03D1/2245 , H04B5/0031 , H04L25/06 , H04L27/06 , H04L27/2335 , H04W4/80
摘要： A demodulator including a peak sampler to control an ADC or a digital resampler to sample a carrier signal in an unmodulated state at peaks, and to sample the carrier signal in a modulated state at a phase of the unmodulated state; and an envelope builder to determine an envelope signal based on differentials between maximum and minimum peaks of respective cycles of the sampled carrier signal. Further, a demodulator having an offset estimator to estimate in-phase and quadrature components of a carrier signal in an unmodulated state to determine in-phase and quadrature component offsets; a load modulated signal estimator to estimate in-phase and quadrature components of a load modulated signal by removing the in-phase and quadrature component offsets from in-phase and quadrature component samples of the carrier signal; and an envelope builder to build an envelope signal by combining the in-phase and quadrature components of the load modulated signal.
摘要翻译： 一种解调器，包括：峰值采样器，用于控制ADC或数字重采样器在峰值处对未调制状态的载波信号进行采样;以及在未调制状态的相位处以调制状态对载波信号进行采样; 以及包络建立器，用于基于采样的载波信号的各个周期的最大和最小峰值之间的差来确定包络信号。 此外，解调器具有偏移估计器，用于估计处于未调制状态的载波信号的同相和正交分量，以确定同相和正交分量偏移; 负载调制信号估计器，用于通过从载波信号的同相和正交分量采样中去除同相和正交分量偏移来估计负载调制信号的同相和正交分量; 以及包络生成器，用于通过组合负载调制信号的同相和正交分量来构建包络信号。
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公开(公告)号：EP0783794A1
公开(公告)日：1997-07-16
申请号：EP95929779.0
申请日：1995-09-08
申请人： Blaupunkt-Werke GmbH
发明人： CHAHABADI, Djahanyar
CPC分类号： H04H20/49 , H03D1/2209 , H04S1/007
摘要： Described is an amplitude demodulator for demodulating a quadrature-modulated stereo signal for radio receivers. The invention calls for a digital intermediate-frequency signal to be generated from the received signal. The digital intermediate-frequency signal is transposed into the baseband signal, two orthogonal components being thus formed. From these two orthogonal components, a magnitude signal and a phase signal are derived. The tangent of the phase signal is determined and the tangent is multiplied by the magnitude signal to give a stereo difference signal.
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公开(公告)号：EP0316952A3
公开(公告)日：1989-09-20
申请号：EP88119243.9
申请日：1988-11-18
IPC分类号： H03D1/22
CPC分类号： H03D1/2236 , H03D1/2209
摘要： A stereo demodulator of a matrix system comprises: a first amplifier (23, 24, 25) for negative feedback amplification of a stereophonic composite signal, a first voltage-current converter (26) for detecting a current-form stereophonic sum signal responsive to a voltage output of the first amplifier, a non-inversion amplifier (27) for negative feedback non-inversion amplification of the stereophonic composite signal, an inversion amplifier (28) for negative feedback inversion amplification of the stereophonic composite signal, a second voltage-current converter (29, 38) for outputting a first current-form stereophonic subchannel signal responsive to a voltage output of the non-inversion amplifier (27), a third voltage-current converter (30, 39) for supplying a current-form signal stereophonic subchannel signal responsive to a voltage output from the inversion amplifier (28), a difference signal demodulator (31) for providing stereophonic difference signals of opposite phases in the form of current signals from the outputs of the second and third voltage-current converters, and a matrix circuit (41) for performing matrix processing on the received stereophonic sum signal from the first voltage-current converter and the stereophonic difference signals from the difference signal demodulator (31) and outputting right and left stereophonic signals in a voltage signal form.
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公开(公告)号：EP1417771B1
公开(公告)日：2008-11-05
申请号：EP02794757.1
申请日：2002-08-06
CPC分类号： H03D1/2209 , H04B1/1646 , H04H40/63
摘要： An arrangement for decoding a stereo multiplex signal, comprising a baseband sum signal (L+R), a difference signal (L-R) which is amplitude-modulated on a suppressed sub-carrier and a pilot signal having a frequency located between the frequency bands of said sum and difference signals, said arrangement having an input for the stereo multiplex signal coupled through parallel stereo sum and difference signal paths to first and second inputs of a dematrix circuit, a synchronous demodulator being included in the difference signal path, a local sinusoidal sub-carrier being supplied to a carrier input of said synchronous demodulator for a synchronous demodulation of said amplitude-modulated difference signal (L-R) into baseband. To maximize stereo channel separation the arrangement is provided with an automatic gain control loop comprising a first mixer stage receiving a reference signal, a signal output thereof being coupled to a second mixer stage, both mixer stages having carrier inputs being supplied with said local sinusoidal sub-carrier for a respective up and down conversion of said reference signal, a signal output of said second mixer stage being coupled through a 6 dB attenuator to a difference circuit providing the difference between the output signal of the attenuator and the reference signal, said difference circuit being coupled to a control input of gain controlled amplifying means for varying the gain of said synchronous demodulator and said first and second mixer stages.
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公开(公告)号：EP1417771A1
公开(公告)日：2004-05-12
申请号：EP02794757.1
申请日：2002-08-06
CPC分类号： H03D1/2209 , H04B1/1646 , H04H40/63
摘要： An arrangement for decoding a stereo multiplex signal, comprising a baseband sum signal (L+R), a difference signal (L-R) which is amplitude-modulated on a suppressed sub-carrier and a pilot signal having a frequency located between the frequency bands of said sum and difference signals, said arrangement having an input for the stereo multiplex signal coupled through parallel stereo sum and difference signal paths to first and second inputs of a dematrix circuit, a synchronous demodulator being included in the difference signal path, a local sinusoidal sub-carrier being supplied to a carrier input of said synchronous demodulator for a synchronous demodulation of said amplitude-modulated difference signal (L-R) into baseband. To maximize stereo channel separation the arrangement is provided with an automatic gain control loop comprising a first mixer stage receiving a reference signal, a signal output thereof being coupled to a second mixer stage, both mixer stages having carrier inputs being supplied with said local sinusoidal sub-carrier for a respective up and down conversion of said reference signal, a signal output of said second mixer stage being coupled through a 6 dB attenuator to a difference circuit providing the difference between the output signal of the attenuator and the reference signal, said difference circuit being coupled to a control input of gain controlled amplifying means for varying the gain of said synchronous demodulator and said first and second mixer stages.
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公开(公告)号：EP1284542A1
公开(公告)日：2003-02-19
申请号：EP01203048.2
申请日：2001-08-12
CPC分类号： H03D1/2209 , H04B1/1646 , H04H40/63
摘要： An arrangement for decoding a stereo multiplex signal, comprising a baseband sum signal (L+R), a difference signal (L-R) which is amplitude-modulated on a suppressed sub-carrier and a pilot signal having a frequency located between the frequency bands of said sum and difference signals, said arrangement having an input for the stereo multiplex signal coupled through parallel stereo sum and difference signal paths to first and second inputs of a dematrix circuit, a synchronous demodulator being included in the difference signal path, a local sinusoidal sub-carrier being supplied to a carrier input of said synchronous demodulator for a synchronous demodulation of said amplitude-modulated difference signal (L-R) into baseband. To maximize stereo channel separation the arrangement is provided with an automatic gain control loop comprising a first mixer stage receiving a reference signal, a signal output thereof being coupled to a second mixer stage, both mixer stages having carrier inputs being supplied with said local sinusoidal sub-carrier for a respective up and down conversion of said reference signal, a signal output of said second mixer stage being coupled through a 6 dB attenuator to a difference circuit providing the difference between the output signal of the attenuator and the reference signal, said difference circuit being coupled to a control input of gain controlled amplifying means for varying the gain of said synchronous demodulator and said first and second mixer stages.
摘要翻译： 一种用于解码立体声多路复用信号的装置，包括基带和信号（L + R），在抑制子载波上幅度调制的差分信号（LR）和具有频率位于 所述和差和差分信号，所述装置具有通过并行立体声和信号路径耦合到立体声多路复用信号的输入，并将差分信号路径耦合到雷达矩阵电路的第一和第二输入，同步解调器包括在差信号路径中，局部正弦子 载波被提供给所述同步解调器的载波输入，用于将所述幅度调制差分信号（LR）同步解调成基带。 为了最大化立体声通道分离，该装置具有自动增益控制回路，该自动增益控制回路包括接收参考信号的第一混频器级，其信号输出耦合到第二混频器级，两个混频器级具有载波输入，所述混频器级被提供有所述局部正弦子 载波用于所述参考信号的相应的上下转换，所述第二混频器级的信号输出通过6dB衰减器耦合到差分电路，差分电路提供衰减器的输出信号与参考信号之间的差，所述差 电路耦合到增益控制放大装置的控制输入端，用于改变所述同步解调器和所述第一和第二混频器级的增益。
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公开(公告)号：EP0783794B1
公开(公告)日：1998-12-02
申请号：EP95929779.7
申请日：1995-09-08
申请人： Blaupunkt-Werke GmbH
发明人： CHAHABADI, Djahanyar
IPC分类号： H03D1/22
CPC分类号： H04H20/49 , H03D1/2209 , H04S1/007
摘要： Described is an amplitude demodulator for demodulating a quadrature-modulated stereo signal for radio receivers. The invention calls for a digital intermediate-frequency signal to be generated from the received signal. The digital intermediate-frequency signal is transposed into the baseband signal, two orthogonal components being thus formed. From these two orthogonal components, a magnitude signal and a phase signal are derived. The tangent of the phase signal is determined and the tangent is multiplied by the magnitude signal to give a stereo difference signal.
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公开(公告)号：EP3226433A2
公开(公告)日：2017-10-04
申请号：EP17158554.0
申请日：2017-02-28
申请人： Intel IP Corporation
发明人： ZHU, Jie , FIEVET, Sebastien , KUTTAN, Sathish K.
CPC分类号： H04B5/02 , H03D1/2209 , H03D1/2245 , H04B5/0031 , H04L25/06 , H04L27/06 , H04L27/2335 , H04W4/80
摘要： A demodulator including a peak sampler to control an ADC or a digital resampler to sample a carrier signal in an unmodulated state at peaks, and to sample the carrier signal in a modulated state at a phase of the unmodulated state; and an envelope builder to determine an envelope signal based on differentials between maximum and minimum peaks of respective cycles of the sampled carrier signal. Further, a demodulator having an offset estimator to estimate in-phase and quadrature components of a carrier signal in an unmodulated state to determine in-phase and quadrature component offsets; a load modulated signal estimator to estimate in-phase and quadrature components of a load modulated signal by removing the in-phase and quadrature component offsets from in-phase and quadrature component samples of the carrier signal; and an envelope builder to build an envelope signal by combining the in-phase and quadrature components of the load modulated signal.
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公开(公告)号：EP1690334B1
公开(公告)日：2007-09-05
申请号：EP04819650.5
申请日：2004-12-01
IPC分类号： H03D1/22
CPC分类号： H03D1/2209
摘要： Multiplier device comprising first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS1 to MSn with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of said multiplier device according to the invention, n is greater than 2, outputs of said multipliers M1 to Mn are respectively coupled through weighting circuits W1 to Wn with respective fixed weighting factors WF1 to WFn to an adder circuit, said mixing signals MS1 to MSn having respective phase angles φi corresponding to φ i = i * Δφ, said weighting factors WFi corresponding to the sine value of said respective phase angles φ i = i * Δφ with Δφ being the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n + 1) and i varying from 1 to n.
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