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    HYBRID AMPLIFIER
    1.
    发明公开
    HYBRID AMPLIFIER 审中-公开
    HYBRIDVERSTÄRKER

    公开(公告)号：EP2944026A1

    公开(公告)日：2015-11-18

    申请号：EP14702373.3

    申请日：2014-01-10

    申请人： Qualcomm Incorporated

    发明人： RAJAEE, Omid

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F2203/45301 ,  H03F2203/45311 ,  H03F2203/45371 ,  H03F2203/45661

    摘要： Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input. The amplifier may further include a cascode circuit including a first pair of transistors coupled to the at least one transistor of the differential pair to form a first plurality of current paths configured to generate a first output. The cascode circuit maymo also include a second pair of transistors coupled to the at least one other transistor of the differential pair to form a second plurality of currents paths configured to generate a second output.

    DIFFERENTIAL AMPLIFIER
    3.
    发明公开
    DIFFERENTIAL AMPLIFIER 失效
    差分放大器。

    公开(公告)号：EP0635173A1

    公开(公告)日：1995-01-25

    申请号：EP93904195.0

    申请日：1993-02-15

    申请人： THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNIC MAJESTY'S GOVERNMENT OF THE UNITED KINGDOM OF GREAT BRITAIN AND

    发明人： COLLINS, Stephen

    IPC分类号： H03F3

    CPC分类号： H03F3/45753 ,  H03F3/45479 ,  H03F3/45771 ,  H03F2203/45341 ,  H03F2203/45474 ,  H03F2203/45661

    摘要： A differential amplifier (10) incorporates five metal oxide field effect transistors (MOSFETs) (M1 to M5). The transistors (M1 to M5) are a source-coupled pair of input transistors (M1, M2) with sources connected to a current control transistor (M5) and having respective drain load transistors (M3, M4). The transistors (M1 to M5) have floating gates (F1 to F5) and input gates (G1 to G5). The amplifier (10) is adjusted to counteract differing input transistor threshold voltage by charging one of the input transistor floating gates (G1, G2) to reduce amplifier offset voltage extrapolated to zero input transistor drain current. It is then adjusted to reduce discrepancies between actual and design values of input transistor drain voltage by charging one or both of the drain load transistor floating gates (F3, F4). The amplifier may be arranged as an operational amplifier (20) with a second stage (16) connected to an input transistor drain. The operational amplifier input offset voltage is determined by comparing the second stage output with a reference and feeding a resulting difference signal to the amplifier input. The input offset voltage is then counteracted by charging an input transistor floating gate (F1 or F2) to reduce the difference signal.