公开(公告)号：EP3525341B8

公开(公告)日：2024-06-12

申请号：EP19156864.1

申请日：2019-02-13

IPC分类号： H03F1/32 ,  H03F1/30 ,  H03F3/45 ,  H03F1/22

CPC分类号： H03F1/223 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/21120130101 ,  H03F1/3276 ,  H03F1/301

公开(公告)号：EP3261250A1

公开(公告)日：2017-12-27

申请号：EP16885458.6

申请日：2016-07-19

申请人： Shenzhen Goodix Technology Co., Ltd.

发明人： ZHANG, Mengwen

IPC分类号： H03F3/45

CPC分类号： H03F1/0205 ,  H03F1/301 ,  H03F1/32 ,  H03F3/005 ,  H03F3/187 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45192 ,  H03F3/45475 ,  H03F3/45659 ,  H03F3/45699 ,  H03F3/45762 ,  H03F2200/129 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/252 ,  H03F2200/264 ,  H03F2200/471 ,  H03F2200/555 ,  H03F2203/45008 ,  H03F2203/45012 ,  H03F2203/45024 ,  H03F2203/45028 ,  H03F2203/45054 ,  H03F2203/45068 ,  H03F2203/45082 ,  H03F2203/45112 ,  H03F2203/45134 ,  H03F2203/45136 ,  H03F2203/45171 ,  H03F2203/45174 ,  H03F2203/45182 ,  H03F2203/45188 ,  H03F2203/45192 ,  H03F2203/45208 ,  H03F2203/45244 ,  H03F2203/45332 ,  H03F2203/45421 ,  H03F2203/45434 ,  H03F2203/45444 ,  H03F2203/45512 ,  H03F2203/45514 ,  H03F2203/45534 ,  H03F2203/45544 ,  H03F2203/45546 ,  H03F2203/45551 ,  H03F2203/45586 ,  H03F2203/45588 ,  H03F2203/45616 ,  H03F2203/45632 ,  H03F2203/45642 ,  H03F2203/45656 ,  H03F2203/45674 ,  H03F2203/45676

摘要： The present application provides an amplifying circuit comprising a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage, the common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage, the common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit provided in the present application can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

摘要翻译： 本申请提供一种放大电路，包括参考电压产生电路，共模电压转换电路，共模负反馈电路和放大子电路。 参考电压产生电路根据后级共模电压产生第一参考电压，第二参考电压和参考共模电压，共模电压转换电路将前级输出差分信号转换为 根据所述参考共模电压产生差分输入信号，所述共模负反馈电路产生控制电压以快速建立所述放大子电路的共模负反馈，其中，所述第一参考电压和所述第二参考电压 被用于消除前级输出差分信号的基线信号。 本申请提供的放大电路可以消除基线信号，转换共模电压，快速建立共模负反馈。

公开(公告)号：EP3231087A1

公开(公告)日：2017-10-18

申请号：EP15790771.8

申请日：2015-10-26

申请人： Qualcomm Incorporated

发明人： ZHOU, Qubo

IPC分类号： H03F3/45 ,  H03F1/08

CPC分类号： H03F3/45179 ,  H03F1/086 ,  H03F3/45188 ,  H03F2200/45 ,  H03F2203/45024 ,  H03F2203/45034 ,  H03F2203/45058 ,  H03F2203/45194 ,  H03F2203/45296 ,  H03F2203/45631 ,  H03M3/458

摘要： A method and an apparatus relating to an amplifier (e.g., an operational transconductance amplifier or OTA) are provided. The OTA includes a first node and a second node. The OTA further includes a differential transistor pair for receiving an input. The differential transistor pair is coupled to the first node and the second node. The OTA includes a pair of output nodes for outputting a response to the input. The response at the pair of output nodes includes a first frequency pole. A capacitive element is coupled between the first node and the second node. The response includes a second frequency pole based on the capacitive element. The second frequency pole is at a greater frequency than the first frequency pole.

摘要翻译： 提供了与放大器（例如，运算跨导放大器或OTA）有关的方法和装置。 OTA包括第一节点和第二节点。 OTA还包括用于接收输入的差分晶体管对。 差分晶体管对耦合到第一节点和第二节点。 OTA包括一对输出节点，用于输出对输入的响应。 该对输出节点处的响应包括第一频率极点。 电容元件耦合在第一节点和第二节点之间。 该响应包括基于电容元件的第二频率极点。 第二频率极点的频率比第一频率极点的频率更高。

公开(公告)号：EP3228002A1

公开(公告)日：2017-10-11

申请号：EP15825667.7

申请日：2015-12-04

申请人： Analog Devices, Inc.

发明人： SHARMA, Yogesh Jayaraman ,  FIORENZA, James

IPC分类号： H03F3/45 ,  G05F3/26

CPC分类号： H03K17/6871 ,  H01L27/088 ,  H01L29/2003 ,  H03F3/45188 ,  H03F3/45385 ,  H03F2200/303 ,  H03F2200/75 ,  H03F2203/45036 ,  H03F2203/45182 ,  H03F2203/45184 ,  H03F2203/45188 ,  H03F2203/45202 ,  H03F2203/45208 ,  H03F2203/45224 ,  H03F2203/45656 ,  H03F2203/45674 ,  H03F2203/45676 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/45722

摘要： A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

摘要翻译： 公开了一种差分对增益级。 在一个实施例中，增益级包括差分耗尽型晶体管对，其包括第一和第二n型晶体管。 在本发明的某些实施例中，耗尽型晶体管可以是GaN（氮化镓）场效应晶体管。 增益级包括有源负载，该有源负载包括电耦合到差分对的耗尽型晶体管的漏极中的至少一个漏极的一个或多个耗尽型晶体管。 有源负载可以包括源极跟随器，用于将差分对的漏极处的AC电压维持在恒定值，并且还可以包括用于设置输出晶体管两端的固定漏极源电压以增加输出阻抗和增益 舞台。

公开(公告)号：EP3213410A1

公开(公告)日：2017-09-06

申请号：EP15778536.1

申请日：2015-09-29

申请人： Qualcomm Incorporated

发明人： CHOKSI, Ojas Mahendra ,  FAN, Bin ,  HANAFI, Bassel

IPC分类号： H03F1/32 ,  H03F1/34 ,  H03F3/193 ,  H03F3/45 ,  H03F3/195

CPC分类号： H03F1/565 ,  H03F1/3211 ,  H03F1/347 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45071 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/301 ,  H03F2200/451 ,  H03F2200/54 ,  H03F2203/21112 ,  H03F2203/45306 ,  H03F2203/45318 ,  H03F2203/45386 ,  H03F2203/45562 ,  H03F2203/45616 ,  H03F2203/45621 ,  H04B1/525

摘要： An apparatus includes: first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal; and a transformer including a primary winding and first and second secondary windings, the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors.

摘要翻译： 一种装置包括：第一和第二晶体管，第一和第二晶体管中的每一个包括栅极端子，源极端子和漏极端子; 以及包括初级绕组以及第一和第二次级绕组的变压器，所述初级绕组耦合到被配置为接收输入信号的第一输入节点和被配置为接收电位的第二输入节点，所述第一和第二次级绕组耦合到 第一和第二晶体管的栅极端子并交叉耦合到第一和第二晶体管的源极端子。

公开(公告)号：EP2854288A3

公开(公告)日：2015-04-29

申请号：EP14191308.7

申请日：2012-07-17

申请人： Ericsson Modems SA

发明人： Lindstrand, Jonas ,  Bryant, Carl ,  Sjöland, Henrik

IPC分类号： H03F1/56 ,  H03F1/52 ,  H03F3/217 ,  H03F3/24 ,  H03F3/45

CPC分类号： H03F1/523 ,  H03F1/565 ,  H03F3/2171 ,  H03F3/245 ,  H03F3/45188 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2203/45318 ,  H03F2203/45332 ,  H03F2203/45396 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03H7/38

摘要： A matching unit (200) configured to match a load of an amplifier circuit to an external circuit. The matching unit (200) comprises a first reactance configured to generate a first positive reactance at low frequencies and a second positive reactance at high frequencies. A second reactance unit comprises at least one series capacitor (C s ) and at least one series inductor (L s ) serially coupled between a resistor (R L ) and the first and second outputs of the amplifier. The second reactance unit is configured to generate a negative reactance at low frequencies and a third positive reactance at high frequencies; and a third reactance unit configured to generate a short at high frequencies so as to reduce a parasitic capacitance at the first and second outputs of the amplifier at high frequencies, wherein said first, second, and third reactance units are configured to operate together to provide a generally constant impedance across a wideband frequency range.

摘要翻译： 匹配单元（200），被配置为将放大器电路的负载匹配到外部电路。 匹配单元（200）包括被配置为产生低频下的第一正电抗和高频下的第二正电抗的第一电抗。 第二电抗单元包括串联耦合在电阻器（RL）与放大器的第一和第二输出端之间的至少一个串联电容器（Cs）和至少一个串联电感器（Ls）。 第二电抗单元被配置为产生低频负电抗和高频第三正电抗; 以及第三电抗单元，所述第三电抗单元被配置为在高频下产生短路以便以高频率减小放大器的第一和第二输出处的寄生电容，其中所述第一，第二和第三电抗单元被配置为一起操作以提供 宽带频率范围内的阻抗通常恒定。

公开(公告)号：EP1875605B1

公开(公告)日：2014-09-03

申请号：EP06751524.7

申请日：2006-04-25

申请人： Intel Corporation

发明人： CHANG, Yuyu

IPC分类号： H03F3/45 ,  H03F3/193

CPC分类号： H03F3/193 ,  H03F3/45188 ,  H03F2200/294 ,  H03F2203/45386 ,  H03F2203/45621 ,  H03F2203/45731

公开(公告)号：EP2522073A4

公开(公告)日：2014-06-11

申请号：EP11790125

申请日：2011-02-11

申请人： NEWLANS INC ,  GUPTA DEV V ,  LAI ZHIGUO

发明人： GUPTA DEV V ,  LAI ZHIGUO

IPC分类号： H03F3/45 ,  H03F1/22 ,  H03H11/04 ,  H03H11/24 ,  H04L25/03

CPC分类号： H03F3/45183 ,  H03F1/223 ,  H03F3/19 ,  H03F3/45188 ,  H03F3/45197 ,  H03F3/45201 ,  H03F2200/264 ,  H03F2200/36 ,  H03F2203/45318 ,  H03F2203/45374 ,  H03F2203/45644 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03H7/24 ,  H03H7/25 ,  H03H7/482 ,  H03H7/487 ,  H03H11/1256 ,  H03H11/53 ,  H03H2210/017 ,  H03H2210/021 ,  H03H2210/028 ,  H03H2210/036 ,  H03H2210/04

公开(公告)号：EP2544367A2

公开(公告)日：2013-01-09

申请号：EP12171149.3

申请日：2012-06-07

申请人： Semiconductor Components Industries, LLC

发明人： Onishi, Akinobu ,  Hinokuma, Yasuhiro ,  Kobayashi, Kazuyuki ,  Murase, Kengo

IPC分类号： H03F3/45

CPC分类号： H03F3/45188

摘要： A semiconductor integrated circuit that is efficiently reduced in a noise level is offered. P-channel type MOS transistors M1 and M2 serving as differential input transistors have a thin gate oxide film in order to reduce the noise level. A protection circuit to protect the P-channel type MOS transistors M1 and M2 from overvoltage is formed including P-channel type MOS transistors M3 and M4. The P-channel type MOS transistor M3 is a first protection transistor to protect the P-channel type MOS transistor M1 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M1. The P-channel type MOS transistor M4 is a second protection transistor to protect the P-channel type MOS transistor M2 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M2.

摘要翻译： 提供了可以有效降低噪声水平的半导体集成电路。 作为差分输入晶体管的P沟道型MOS晶体管M1和M2具有薄的栅极氧化膜，以便降低噪声水平。 形成保护P沟道型MOS晶体管M1和M2免受过电压的保护电路，包括P沟道型MOS晶体管M3和M4。 P沟道型MOS晶体管M3是用于保护P沟道型MOS晶体管M1免受过电压的第一保护晶体管，并连接到P沟道型MOS晶体管M1的漏极。 P沟道型MOS晶体管M4是用于保护P沟道型MOS晶体管M2免受过电压的第二保护晶体管，并且连接到P沟道型MOS晶体管M2的漏极。

公开(公告)号：EP2351210A1

公开(公告)日：2011-08-03

申请号：EP09792615.8

申请日：2009-09-16

申请人： QUALCOMM Incorporated

发明人： ELLERSICK, William F.

IPC分类号： H03F1/52 ,  H03F3/45 ,  H03G11/00

CPC分类号： H03F3/45188 ,  H03F1/523 ,  H03F3/45677 ,  H03F2200/426 ,  H03F2200/441 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/462 ,  H03F2200/66 ,  H03F2203/45186 ,  H03F2203/45354 ,  H03F2203/45636 ,  H03F2203/45641 ,  H03F2203/45674 ,  H03G11/002 ,  H03G11/02

摘要： An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.