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    DEVICE AND METHOD FOR PHOTON DETECTION
    1.
    发明公开
    DEVICE AND METHOD FOR PHOTON DETECTION 审中-公开
    设备，设备和方法

    公开(公告)号：EP2740216A2

    公开(公告)日：2014-06-11

    申请号：EP12754069.8

    申请日：2012-08-02

    申请人： Base4 Innovation Ltd

    发明人： ISAAC, Thomas Henry

    IPC分类号： H03K5/08 ,  H03K5/15 ,  H03K5/19 ,  G01T1/24

    CPC分类号： H03K5/125 ,  G01N21/01 ,  G01T1/248 ,  H03K5/082 ,  H03K5/15073 ,  H03K5/19

    摘要： A device (10) for determining the number of discrete events represented by an input signal is provided. The input signal may, for example, comprise pulses representing photons arriving at a detector. The device (10) may comprise a plurality, n, of comparator circuits (14) for reading the signal. For each comparator circuit (14) from i=1 to i=n, the i
    th comparator circuit (14) has a corresponding threshold value which the amplitude of a pulse representing i discrete events will exceed, but which the amplitude of a pulse representing i-1 discrete events will not exceed. Each comparator circuit (14) is arranged to output a first value when the input signal exceeds its threshold value and a second value when the input signal is less than its threshold value. The device (10) includes a counter (16) for counting the number of outputs of the first value that have been output by the plurality of comparator circuits (14).

    Controlled delay digital clock signal generator
    2.
    发明公开
    Controlled delay digital clock signal generator 失效
    数字仪器仪表仪器Verzögerung。

    公开(公告)号：EP0603077A1

    公开(公告)日：1994-06-22

    申请号：EP93403059.4

    申请日：1993-12-16

    申请人： TEXAS INSTRUMENTS FRANCE ,  TEXAS INSTRUMENTS INCORPORATED

    发明人： Carbou, Pierre ,  Guignon, Pascal

    IPC分类号： H03K5/15 ,  H03K4/00

    CPC分类号： H03K4/00 ,  H03K5/15073

    摘要： Controlled delay digital clock signal generator, characterized in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

    摘要翻译： 控制延迟数字时钟信号发生器，其特征在于它包括从时钟信号（CK）及其互补信号（CK）产生的装置（I5，I6，I7，I8，I9，I10，IT7，IT8，IT9，IT10，C4） CKB）包括至少两个正斜率段和至少两个负斜率段的斜坡信号，所述斜坡信号装置（I1，I2，IT1，IT2，IT3，C2，CET1T2，AMPLI，I3，I4，IT4，IT5，IT6， C3，CET3T4，AMPL2），用于单独控制所述段的斜率的装置，具有用于将斜坡信号（RAMP）转换成方波信号（CKQ）的触发电路（AMPLO）装置（NO0，A0，A1，NO1） 实现与时钟信号（CK）的转换和所述时钟信号的时钟互补时钟信号（CKB）产生的延迟平方时信号（CKQ）的逻辑组合，以获得与斜坡信号相同的延迟的数字时钟信号 有不同坡度的段。

    Multiple phase clock generator
    3.
    发明公开
    Multiple phase clock generator 失效
    多相时钟发生器

    公开(公告)号：EP0307572A3

    公开(公告)日：1990-03-14

    申请号：EP88111139.7

    申请日：1988-07-12

    申请人： TEKTRONIX, INC.

    发明人： Traa, Einar Oddbjorn

    IPC分类号： G06F1/04 ,  H03K5/15

    CPC分类号： H03K5/15073 ,  H03K17/007 ,  H03K17/603 ,  H03K17/6292

    摘要： A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the mas­ter clock signal causes a next phase cell on the ring to supply its phased clock output signal.

    Multiple phase clock generator
    5.
    发明公开
    Multiple phase clock generator 失效
    Mehrphasiger Taktgenerator。

    公开(公告)号：EP0307572A2

    公开(公告)日：1989-03-22

    申请号：EP88111139.7

    申请日：1988-07-12

    申请人： TEKTRONIX, INC.

    发明人： Traa, Einar Oddbjorn

    IPC分类号： G06F1/04 ,  H03K5/15

    CPC分类号： H03K5/15073 ,  H03K17/007 ,  H03K17/603 ,  H03K17/6292

    摘要： A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the mas­ter clock signal causes a next phase cell on the ring to supply its phased clock output signal.

    摘要翻译： 多相时钟发生器包括偶数个相位单元的环，每个相位单元产生单独的相位时钟信号。 响应于来自环上的前一相位单元的使能信号和预偏置输出信号的同时断言，每相单元提供其相位时钟信号和预偏置输出信号。 响应于主时钟信号中的状态变化，提供给环周围的每个相位单元的使能信号被断言并且被断言，允许同时提供提供给非相邻相位单元的信号。 当使用一个相位单元来初始化其相位时钟信号和预偏置输出信号时，主时钟信号的每个转换使得环上的下一个相位单元提供其相位时钟输出信号。

    CIRCUIT DE GÉNÉRATION D'AU MOINS DEUX SIGNAUX RECTANGULAIRES À DÉPHASAGE RÉGLABLE ET UTILISATION DUDIT CIRCUIT
    6.
    发明公开
    CIRCUIT DE GÉNÉRATION D'AU MOINS DEUX SIGNAUX RECTANGULAIRES À DÉPHASAGE RÉGLABLE ET UTILISATION DUDIT CIRCUIT 有权
    电路，用于生成与可调式相移，并使用该电路的至少两个正方形状信号

    公开(公告)号：EP3090487A1

    公开(公告)日：2016-11-09

    申请号：EP14815311.7

    申请日：2014-12-15

    申请人： THALES

    发明人： GUEPRATTE, Kevin ,  LE BARS, David ,  STEPHAN, Hervé

    IPC分类号： H03K5/15

    CPC分类号： H03K5/15 ,  H03K5/15066 ,  H03K5/15073

    摘要： The present invention relates to a circuit (40) for generating at least two rectangular signals (S
    1 , S
    2 ) with adjustable phase shift comprising a frequency divider circuit (46) receiving a clock signal (CLK) as input and supplying a signal (CLK_2) as output, at least two comparators (C1, C2), respectively receiving a first threshold voltage (Vs
    1 ) and at least one second threshold voltage (Vs
    2 ) on one input, and a ramp signal synchronised with the clock signal on a second input, the at least two threshold voltages making it possible to adjust the value of the phase shift between the at least two rectangular signals and at least two D-type switches (D1, D2) respectively receiving the output signal (Cmp1) from the first comparator and the output signal (Cmp2) from the second comparator on the clock inputs thereof, and the output signal of the frequency divider circuit on the "D" input thereof.

    摘要翻译： 一种用于生成具有可调节的相移的至少两个矩形信号的电路，包括：分频电路做了接收时钟信号作为输入，并提供一个信号作为输出，所述至少两个比较器并分别接收第一阈值电压和至少一个 在一个输入第二阈值电压和斜坡信号，与时钟信号同步，在第二输入中，所述至少两个阈值电压允许所述至少两个矩形信号之间的相移的值进行调整，并且至少 两个D型触发器并分别接收来自第一比较器的输出信号和来自第二比较器在它们的时钟输入端的输出信号，和从在其D输入端的分频电路的输出信号。