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公开(公告)号：EP1869772A1
公开(公告)日：2007-12-26
申请号：EP06727754.1
申请日：2006-03-28
申请人： NXP B.V.
IPC分类号： H03M1/18
摘要： A device is for digitally processing an input signal that is susceptible to variations in signal strength. The signal (48) is analog to digital converted into a bitstream signal (47), the bitstream signal representing the input signal by consecutive digital values. The device has a signal strength detection circuit (32) for generating a control signal indicative for an overload condition in which the signal strength exceeds a input range of the analog to digital converter, e.g. a sigma-delta modulator. The signal strength detection circuit detects, in the bitstream signal, a sequence (49,50) of adjacent and equal digital values, the sequence having at least a predetermined length. The circuit detects the overload condition effectively and fast, avoiding the delay of signal strength detection in a digital processor.
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2.发明公开
公开(公告)号：EP2324573A1
公开(公告)日：2011-05-25
申请号：EP08796853.3
申请日：2008-07-30
申请人： Micro Motion, Inc.
IPC分类号： H03M3/02
摘要： A delta-sigma modulator (100) including a dithering capability for eliminating idle tones is provided according to the invention. The delta-sigma modulator (100) includes a bitstream converter (107) configured to generate a digital signal output substantially corresponding to an analog signal input, a periodicity detector (111) coupled to the bitstream converter (107) and configured to detect periodicity in the digital signal output, and a dithering sequence generator (116) connected to and activated by the periodicity detector (111). The dithering sequence generator (116) generates a dithering sequence. The delta-sigma modulator (100) further includes a pulse-width modulation (PWM) generator (119) coupled to the dithering sequence generator (116) and receiving the dithering sequence. The PWM generator (119) modulates the dithering sequence onto the analog signal input of the delta-sigma modulator (100) as a dithering signal.
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公开(公告)号：EP1911163B1
公开(公告)日：2010-01-13
申请号：EP06744355.6
申请日：2006-06-29
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037
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公开(公告)号：EP0764368A1
公开(公告)日：1997-03-26
申请号：EP95920120.0
申请日：1995-06-01
发明人： HEIKKILÄ, Juha , LIPASTI, Lauri
IPC分类号： H03M3
摘要： The invention relates to an oversampled high-order modulator, especially a sigma-delta modulator, comprising cascaded integrators (H1, H2, ...HN) in a number corresponding to the order of the modulator, a quantizer (15), and a negative feedback (21, 22, 23, 24). The problem with the high-order modulators is that the modulator is locked in an unstable mode from which it should be restored without considerably interfering with the operation of the modulator. The invention achieves this by temporarily changing the value of the negative feedback to a direction which whill restore the stable operation.
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5.发明授权
公开(公告)号：EP2324573B1
公开(公告)日：2013-01-23
申请号：EP08796853.3
申请日：2008-07-30
申请人： Micro Motion, Inc.
IPC分类号： H03M3/02
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公开(公告)号：EP1911163A1
公开(公告)日：2008-04-16
申请号：EP06744355.6
申请日：2006-06-29
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037
摘要： A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behaviour has been observed, and major changes to design are not normally required to implement the detection mechanism.
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公开(公告)号：EP0764368B1
公开(公告)日：2000-05-03
申请号：EP95920120.3
申请日：1995-06-01
申请人： ATMEL CORPORATION
发明人： HEIKKILÄ, Juha , LIPASTI, Lauri
IPC分类号： H03M3/02
摘要： The invention relates to an oversampled high-order modulator, especially a sigma-delta modulator, comprising cascaded integrators (H1, H2, ...HN) in a number corresponding to the order of the modulator, a quantizer (15), and a negative feedback (21, 22, 23, 24). The problem with the high-order modulators is that the modulator is locked in an unstable mode from which it should be restored without considerably interfering with the operation of the modulator. The invention achieves this by temporarily changing the value of the negative feedback to a direction which whill restore the stable operation.
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