公开(公告)号：EP4372993A1

公开(公告)日：2024-05-22

申请号：EP23159308.8

申请日：2023-03-01

Applicant: Hyundai Mobis Co., Ltd.

Inventor： YANG, Su Hun

IPC: H03M3/00 ,  G01R31/3835

CPC classification number: H03M3/438 ,  H03M3/466 ,  G01R31/3835

Abstract: Disclosed herein is an apparatus for measuring a voltage including a primary integrator circuit configured to operate as a first integral stage of a sigma-delta analog-to-digital converter (ADC) circuit by a switching according to a control signal of a controller, a secondary integrator circuit configured to operate as a second integral stage by a switching of the controller, a comparator configured to compare final voltages modulated through the primary integrator circuit and the secondary integrator circuit, and a digital filter configured to delay an output of the comparator by a specified number of clocks according to a switching of the controller, pass the delayed output through a digital-to-analog converter (DAC) to feed the delayed output back to the primary and secondary integrator circuits, and receive the delayed output signal of the comparator as an input, wherein an output of the digital filter becomes a final measured value.

公开(公告)号：EP3410603A1

公开(公告)日：2018-12-05

申请号：EP18173095.3

申请日：2018-05-18

Applicant: Infineon Technologies Austria AG

Inventor： BUFFA, Cesare ,  CARDES GARCIA, Fernando ,  HERNANDEZ-CORPORALES, Luis ,  QUINTERO ALONSO, Andres ,  WIESBAUER, Andreas

IPC: H03M1/60 ,  H03M3/00

CPC classification number: H03M3/496 ,  H03M1/504 ,  H03M1/60 ,  H03M3/438

Abstract: In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.

公开(公告)号：EP3323202A1

公开(公告)日：2018-05-23

申请号：EP16734116.3

申请日：2016-06-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： ZANBAGHI, Ramin ,  BRENNAN, Aaron ,  MELANSON, John, L.

IPC: H03M3/02

CPC classification number: H03M3/438 ,  H03M1/60

Abstract: A delta-sigma modulation analog-to-digital converter (ADC) may be constructed by combining a VCO used for a first order filter with a digital loop filter used for a second or higher order of the ADC. One such ADC would include an analog input node configured to receive an analog signal; a voltage-controlled oscillator (VCO) comprising a first input configured to receive the analog signal, wherein the voltage-controlled oscillator is configured to implement a first order noise-shaping function; a digital loop filter comprising a second input configured to receive an output of the voltage-controlled oscillator (VCO); and a digital output node configured to output a digital signal based on an output of the digital loop filter. The digital loop filter may be configured to implement at least a first order noise-shaping function, but may also implement higher order noise-shaping functions.

公开(公告)号：EP3142259A1

公开(公告)日：2017-03-15

申请号：EP15184979.1

申请日：2015-09-14

Applicant: Nokia Technologies Oy

Inventor： ÖSTMAN, Kim

IPC: H04B1/16 ,  H03M3/00

CPC classification number: H04B1/16 ,  H03M3/43 ,  H03M3/438 ,  H03M3/458

Abstract: There are disclosed various methods and apparatuses for receiving a radio frequency a signal. In some embodiments the method a signal is provided to an input of an amplifying element. An amplified signal is formed on the basis of the input signal by the amplifying element. The amplified signal is integrated by an integrating element to form an integrated signal. A feedback signal is formed on the basis of the integrated signal, wherein the feedback signal is provided to the integrating element. In some embodiments the apparatus comprises means for implementing the method.

Abstract translation: 公开了用于接收射频信号的各种方法和装置。 在一些实施例中，该方法将信号提供给放大元件的输入。 基于放大元件的输入信号形成放大信号。 放大的信号由积分元件积分以形成积分信号。 基于积分信号形成反馈信号，其中反馈信号被提供给积分元件。 在一些实施例中，装置包括用于实现该方法的装置。

公开(公告)号：EP2890015A1

公开(公告)日：2015-07-01

申请号：EP14197322.2

申请日：2014-12-11

Applicant: MediaTek, Inc

Inventor： Huang, Yen-Chuan ,  Lou, Chih-Hong ,  Wang, Chi-Yun ,  Hung, Li-Han ,  Wu, Min-Hua

IPC: H03M3/00

CPC classification number: H03M1/001 ,  H03M1/0626 ,  H03M1/46 ,  H03M3/344 ,  H03M3/37 ,  H03M3/438 ,  H03M3/458

Abstract: An analog-to-digital converting device (100, 200) includes: an integrator (102, 202) arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter (104, 304, 404, 504, 604, 704) arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter (106) arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter (108) arranged to generate the first analog feedback signal according to the digital output signal.

Abstract translation: 模拟数字转换装置（100,200）包括：积分器（102,202），被布置成根据模拟输入信号和第一模拟反馈信号产生积分信号; 布置成根据积分信号产生第一滤波信号的低通滤波器（104,304,404,504,604,704）; 布置成根据第一滤波信号产生数字输出信号的模拟 - 数字转换器（106） 以及第一数模转换器（108），被配置为根据数字输出信号产生第一模拟反馈信号。

公开(公告)号：EP2538562A3

公开(公告)日：2013-01-09

申请号：EP12004634.7

申请日：2012-06-20

Applicant: Linear Technology Corporation

Inventor： Steensgaard-Madsen, Jesper ,  O'Halloran, Micah, Galletta ,  Oprescu, Florin

IPC: H03M1/06 ,  H03M3/02

CPC classification number: H03M1/0682 ,  H03M1/1076 ,  H03M1/468 ,  H03M3/35 ,  H03M3/378 ,  H03M3/438

Abstract: An analog-to-digital converter, ADC, system (200) configured to receive a first (V1) and a second (V2) analog quantity and to provide a plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities. The ADC system includes a first (301), a second (302), and a third (305) ADC circuit, and a digital interface circuit (303). The first ADC circuit (301) is configured to provide a first code (D1) representative of the first analog quantity (V1) and to provide a first analog residue quantity (R1) representative of the first analog quantity (V1) with respect to the first code (D1). The second ADC circuit (302) is configured to provide a second code (D2) representative of the second analog quantity (V2) and to provide a second analog residue quantity (R2) representative of the second analog quantity (V2) with respect to the second code (D2). The third ADC circuit (304) is configured to receive the first (R1) and second (R2)analog residue quantities, and to provide a third digital code (D3) representative of a difference of the first (R1) and second (R2) analog residue quantities. The digital interface circuit (303) is configured to receive the first (D1), second (D2), and third (D3) codes, and to provide the plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities.

公开(公告)号：EP2346167A1

公开(公告)日：2011-07-20

申请号：EP09817375.0

申请日：2009-03-27

Applicant: Panasonic Corporation

Inventor： DOSHO, Shiro ,  MATSUKAWA, Kazuo ,  MITANI, Yosuke

IPC: H03H11/12 ,  H03M3/02

CPC classification number: H03M3/454 ,  H03H11/1252 ,  H03M3/404 ,  H03M3/438

Abstract: Resistive elements (11, 12) and a capacitive element (23) are respectively coupled between a node (101) and an inverting input terminal of an operational amplifier (10), between the node (101) and an output terminal of the operational amplifier (10), and between the node (101) and a common node. A resistive element (14) and a capacitive element (25) are coupled between the node (101) and a signal input terminal. Capacitive elements (21, 22) and a resistive element (13) are respectively coupled between a node (102) and the inverting input terminal of the operational amplifier (10), between the node (102) and the output terminal, and between the node (102) and the common node. Capacitive elements (24, 26) are respectively coupled between the node (102) and the signal input terminal, and the node (102) and the common node. An overall admittance where elements coupled to the node (101) are coupled in parallel is equal to an overall admittance where elements coupled to the node (102) are coupled in parallel.

Abstract translation: 电阻元件（11,12）和电容元件（23）分别耦合在节点（101）和运算放大器（10）的反相输入端之间，节点（101）和运算放大器的输出端 （10），并且在节点（101）和公共节点之间。 电阻元件（14）和电容元件（25）耦合在节点（101）和信号输入端子之间。 电容元件（21,22）和电阻元件（13）分别耦合在节点（102）和运算放大器（10）的反相输入端子之间，在节点（102）和输出端子之间以及 节点（102）和公共节点。 电容元件（24,26）分别耦合在节点（102）和信号输入端，以及节点（102）和公共节点之间。 耦合到节点（101）的元件并联耦合的整体导纳等于耦合到节点（102）的元件并联耦合的整体导纳。

公开(公告)号：EP1668779B1

公开(公告)日：2009-12-02

申请号：EP05741872.5

申请日：2005-04-29

Applicant: Microchip Technology Incorporated

Inventor： QUIQUEMPOIX, Vincent ,  DEVAL, Philippe

IPC: H03M3/00

CPC classification number: H03M3/356 ,  H03M3/43 ,  H03M3/438

公开(公告)号：EP1450490A1

公开(公告)日：2004-08-25

申请号：EP03425094.4

申请日：2003-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cesura, Giovanni ,  Panigada, Andrea ,  Serina, Nadia

IPC: H03M1/06 ,  H03M3/02

CPC classification number: H03M3/356 ,  H03M3/424 ,  H03M3/438

Abstract: An analog-to-digital converter (200) is proposed. The converter includes at least one stage (105) for converting an analog input signal into a digital output signal using a parallel quantizer (115) comparing the analog input signal with a plurality of threshold values in parallel; the converter of the invention further includes, for at least one selected stage (105), means (210,220) for estimating an analog correction signal indicative of the mean value of a quantization error of the selected stage, and means (440i) for at least partially compensating an offset error of the parallel quantizer (105) in the selected stage according to the analog correction signal.

Abstract translation: 提出了一种模数转换器（200）。 转换器包括用于使用并行量化器（115）将模拟输入信号转换为数字输出信号的至少一个级（105），其将模拟输入信号与多个阈值并联进行比较; 本发明的转换器还包括对于至少一个所选择的级（105），用于估计指示所选级的量化误差的平均值的模拟校正信号的装置（210,220），以及用于至少 根据模拟校正信号，在所选择的级中部分地补偿并行量化器（105）的偏移误差。

公开(公告)号：EP1158663A3

公开(公告)日：2004-05-26

申请号：EP01304359.1

申请日：2001-05-16

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Kishida, Masahiro

IPC: H03F3/217

CPC classification number: H03F3/217 ,  H03F2200/331 ,  H03M3/356 ,  H03M3/43 ,  H03M3/438

Abstract: A digital switching amplifier in accordance with the present invention is provided with attenuation sections that attenuate respective 1-bit signals that have been subjected to the power amplification, and an offset voltage addition and adjustment section that adds adjustment voltages to output signals of the respective attenuation sections so that a D.C. voltage level difference between negative feedback signals which return to a delta sigma modulation circuit becomes substantially zero. This allows to ensurely provide a digital switching amplifier that can avoid that the gain with respect to positive and negative input signals change and easily avoid that the noise occurs in the lower frequency band due to an offset voltage.

Abstract translation: 根据本发明的数字开关放大器设置有衰减已经经过功率放大的各个1位信号的衰减部分，以及将调整电压加到相应衰减的输出信号上的偏移电压相加和调整部分 使得返回到Δ-Σ调制电路的负反馈信号之间的直流电压电平差基本为零。 这允许确保提供数字开关放大器，其可以避免相对于正和负输入信号的增益改变并且容易避免由于偏移电压而在较低频带中发生噪声。