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    ANORDNUNG UND VERFAHREN ZUM ERZEUGEN EINES IM WESENTLICHEN SINUSFÖRMIGEN SYNCHRONISATIONSPULSES
    2.
    发明公开
    ANORDNUNG UND VERFAHREN ZUM ERZEUGEN EINES IM WESENTLICHEN SINUSFÖRMIGEN SYNCHRONISATIONSPULSES 审中-公开
    装置和方法，用于产生基本上为正弦同步脉冲

    公开(公告)号：EP2813040A1

    公开(公告)日：2014-12-17

    申请号：EP13701241.5

    申请日：2013-01-21

    申请人： Robert Bosch GmbH

    发明人： NITSCHE, Gerald ,  MOMENI, Massoud

    IPC分类号： H04L25/03 ,  H04L7/04 ,  B60R16/03

    CPC分类号： H04L7/0079 ,  H04L7/0091 ,  H04L25/0286 ,  H04L2007/047

    摘要： The invention relates to a reception arrangement (3) for a control device in a vehicle, comprising a voltage generator (30) for generating a synchronisation pulse, said synchronisation pulse being generated with a predetermined shape and a predetermined time behaviour inside predetermined specification limits, wherein the reception arrangement (3) outputs the synchronisation pulse for synchronising a signal transmission via a data bus (5) to at least one sensor (7). The invention further relates to a method for generating such a synchronisation pulse. According to the invention, the voltage generator (30) comprises a voltage amplifier (36) which, on the basis of a reference voltage (Uref), generates the synchronisation pulse substantially as a sinusoidal oscillation.

    METHOD AND SYSTEM FOR SYNCHRONIZATION IN A FREQUENCY SHIFT KEYING RECEIVER
    4.
    发明公开
    METHOD AND SYSTEM FOR SYNCHRONIZATION IN A FREQUENCY SHIFT KEYING RECEIVER 有权
    方法和系统中的同步FREQUENZUMTASTEMPFÄNGER

    公开(公告)号：EP1611706A4

    公开(公告)日：2008-06-18

    申请号：EP04758291

    申请日：2004-03-24

    申请人： MOTOROLA INC

    发明人： CARSELLO STEPHEN R ,  GOLDBERG MARK A

    IPC分类号： H04L7/00 ,  H04L7/04 ,  H04L7/08 ,  H04L27/00 ,  H04L27/10

    CPC分类号： H04L7/042 ,  H04L7/08 ,  H04L27/10 ,  H04L2007/047 ,  H04L2027/0065 ,  H04L2027/0095

    摘要： The invention provides a method and apparatus for achieving timing synchronization during signal acquisition and for achieving frequency synchronization in a digital communication receiver after signal acquisition. The apparatus comprises: a receiving mechanism adapted to receive a signal containing a plurality of data slots with a sync word within each transmitted data slot; a correlator for forming multiple correlations, each corresponding to a selected sync symbol interval and for correlating the received signal with a sinusoid of an expected frequency for each of the selected sync symbol intervals; a combiner for gathering and combining the multiple correlations over a set of small offset frequencies, according to the FSK modulation index and known sync symbol pattern; a peak detector, which forms a sync correlation signal according to the maximum combiner output amplitude, among the candidate offset frequencies, at each time instant; a threshold detector, which, at each time instant, compares the sync correlation signal to a threshold; a symbol timing estimator, which, upon detecting that the sync correlation has exceeded the threshold, establishes symbol timing in accordance with the peak of the sync correlation signal. The apparatus additionally comprises a frequency offset estimator for formulating an offset estimate using known and estimated symbols and a quality estimating tool for determining a quality of the frequency offset estimate using a signal-to-noise ratio calculation.

    Clock timing recovery methods and circuits
    6.
    发明公开
    Clock timing recovery methods and circuits 失效
    Verfahren und Schaltungen zurTaktrückgewinnung

    公开(公告)号：EP1657846A2

    公开(公告)日：2006-05-17

    申请号：EP06002711.7

    申请日：1997-07-09

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

    发明人： Takao, Toshiaki ,  Shirato, Tadashi ,  Suzuki, Yoshifumi

    IPC分类号： H04L7/02 ,  H04L7/033

    CPC分类号： H04L7/0054 ,  H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/046 ,  H04L2007/047

    摘要： A clock timing recovery circuit comprises clock generating means for generating a system clock which repeats with a fixed period. A phase shift means outputs a first clock, phase-shifted with respect to the system clock, as the clock timing for sampling the baseband signal obtained by detection of the received signal. Control means are provided for controlling the amount of phase shift of the phase shift means. A sampling clock generating means generates a second clock with leading or trailing edge points which lead the leading or trailing edge points of the first clock by a predefined timing difference δt. It also generates a third clock with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock by δt. The control means includes arithmetic means which calculates the amount of phase shift of the phase shift means by comparing information relating to the phase error of the clock timing, the information being obtained respectively from the sampled signals obtained by sampling the baseband signal using the second and third clocks as the respective sampling clocks.

    摘要翻译： 时钟定时恢复电路包括用于产生以固定周期重复的系统时钟的时钟产生装置。 相移装置输出相对于系统时钟相移的第一时钟作为用于对通过检测接收信号获得的基带信号进行采样的时钟定时。 提供控制装置用于控制相移装置的相移量。 采样时钟产生装置产生第二时钟，其中前沿或后沿点将第一时钟的前沿或后沿点引导预定义的定时差。 它还产生第三时钟，其中前沿或后沿点落后于第一时钟的前沿或后沿点之后。 控制装置包括运算装置，它通过比较与时钟定时的相位误差相关的信息来计算相移装置的相移量，该信息分别从通过使用第二基准信号进行采样而获得的采样信号获得， 第三个时钟作为相应的采样时钟。

    METHOD AND SYSTEM FOR SYNCHRONIZATION IN A FREQUENCY SHIFT KEYING RECEIVER
    7.
    发明公开
    METHOD AND SYSTEM FOR SYNCHRONIZATION IN A FREQUENCY SHIFT KEYING RECEIVER 有权
    方法和系统中的同步FREQUENZUMTASTEMPFÄNGER

    公开(公告)号：EP1611706A2

    公开(公告)日：2006-01-04

    申请号：EP04758291.1

    申请日：2004-03-24

    申请人： MOTOROLA, INC.

    发明人： CARSELLO, Stephen, R. ,  GOLDBERG, Mark, A.

    IPC分类号： H04L7/00

    CPC分类号： H04L7/042 ,  H04L7/08 ,  H04L27/10 ,  H04L2007/047 ,  H04L2027/0065 ,  H04L2027/0095

    摘要： The invention provides a method and apparatus for timing and frequency synchronization during and after signal acquisition, respectively, in a digital communication receiver. The apparatus comprises: a receiver (110) receiving a plurality of data slots each containing a sync word (310); a correlator (220) forming multiple correlations of the received signal with a sinusoid of an expected frequency for each of the selected sync symbol intervals; a combiner (240) combining the multiple correlations according to the FSK modulation index ad known sync symbol pattern; a peak detector (230) forming a sync correlation signal of the maximum combiner output amplitude; a threshold detector (250) comparing the sync correlation signal to a threshold; a symbol timing estimator (270) establishing symbol timing based on the peak of the sync correlation signal; a frequency offset estimator (260); and a quality estimator (280) determining a quality of the frequency offset estimate using a SNR calculation.

    Circuit and method for determing the phase difference between a sample clock and a sampled signal by linear approximation
    10.
    发明公开
    Circuit and method for determing the phase difference between a sample clock and a sampled signal by linear approximation 审中-公开
    装置和方法，用于确定与线性近似一个采样时钟和采样信号之间的相位差

    公开(公告)号：EP1126617A3

    公开(公告)日：2003-11-12

    申请号：EP01300806.5

    申请日：2001-01-30

    申请人： STMicroelectronics, Inc.

    发明人： Ozdemir, Hakan

    IPC分类号： H03L7/091 ,  G11B20/14 ,  G11B20/10

    CPC分类号： H04L7/0054 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10296 ,  G11B20/1403 ,  H03L7/091 ,  H04L7/0029 ,  H04L2007/047

    摘要： A phase-calculation circuit (46) includes a buffer (42), an approximation circuit (70), and an interpolator (56). The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit (70) linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator (56) calculates the absolute phase of that sample with respect to a predetermined point of the signal using the relative phase and the values of the first and second samples. The circuit is used to decrease the alignment-acquisition time of a digital timing-recovery loop, and allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. The circuit may determine an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery circuit uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock and reduces the overall alignment-acquisition time.