Abstract:
A method (500) and apparatus (400) of clock harmonic spur removal entails calculating (502) an exact frequency of a clock harmonic spur from Automatic Frequency Control (AFC) values, measuring (504) a spur magnitude and a spur phase of the clock harmonic spur, and canceling (506) a clock harmonic causing the clock harmonic spur and a processor (402) that is operable to perform these functions.
Abstract:
The radio telecommunication terminal (2) comprises a data burst scheduler able to schedule the continuous transmission of consecutive data bursts which generate noise of similar energy on the radio-frequency channel as long as a specific radio-frequency channel is used to receive a radio signal, the respective energy of the noise generated by the transmission of two consecutive first and second data burst being similar only if the noise energy gradient between the end of the transmission of the first data burst and the beginning of the transmission of the second data burst is situated between predetermined upper and lower limits.
Abstract:
This patent disclosure presents circuits, systems and methods to spread a clock signal to produce a random spreading for the clock signal that offers the maximum possible power density reduction for the spurious radiations generated from the clock signal and its harmonics. These new inventions utilize a non-linear feedback control loop to assist in generation of the spread spectrum clock and result in electronic products that can pass the FCC requirements for spurious radiations generated by the clock signal and its harmonics without utilizing expensive shielding and other EMI suppression methods.
Abstract:
A network device for cancelling spurs without affecting an incoming signal. The network device includes an estimator for estimating amplitude and phase of a spur over a predetermined period of time. The network device also includes processing means for freezing further estimation of the amplitude and phase of the spur, for cancelling for an estimated spur and for allowing incoming packets. The network device further includes subtracting means for subtracting the estimated spur from an incoming packet. The estimated spur is subtracted from the incoming packet without affecting incoming signals that are not part of the estimated spur.
Abstract:
The present invention relates to a high speed interface for radio systems, in particular to a synchronous serial digital interface for car radio. In an its embodiment the synchronous serial digital interface for at least dual radio receiver systems comprises a master device and a slave device; said dual radio receiver systems having an intermediate frequency; said master device and said slave device exchange data in bi-directional way on at least one communication channel; said master device and said slave device have a unique bit clock; said master device supply to said slave device a synchronisation signal; said synchronisation signal have frequency spectrum with an amplitude at said intermediate frequency lower than at the other frequencies.