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    CIRCUIT AND METHOD FOR CREDIT-BASED FLOW CONTROL
    1.
    发明公开
    CIRCUIT AND METHOD FOR CREDIT-BASED FLOW CONTROL 审中-公开
    基于信用的流量控制的电路和方法

    公开(公告)号：EP3267305A1

    公开(公告)日：2018-01-10

    申请号：EP17179659.2

    申请日：2017-07-04

    Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives

    Inventor： MIRO PANADES, Ivan

    IPC: G06F3/06 ,  G06F5/10 ,  G06F15/163

    CPC classification number: H04L47/39 ,  G06F3/0656 ,  G06F5/10 ,  G06F5/12 ,  G06F15/163 ,  H04L47/30 ,  H04L47/621 ,  H04L47/6245

    Abstract: The invention concerns a receiving circuit of a communications link comprising: a first data buffer (336) configured to input, under control of a first clock signal (CLK_V"), data of a first data stream transmitted by a transmitting circuit (302), and to generate a credit trigger signal indicating when a data value is read from the first data buffer (336), wherein data is read from the first data buffer (336), or from a further data buffer (338) coupled to the output of the first data buffer (336), under control of a second clock signal (CLK R); and a credit generation circuit (342) configured to generate, based on the credit trigger signal, a credit signal for transmission to the transmitting circuit (302) under control of the first clock signal (CLK_V"), the credit signal indicating that one or more further data values of the first data stream can be transmitted by the transmitting circuit.

    Abstract translation: 本发明涉及一种通信链路的接收电路，包括：第一数据缓冲器（336），被配置为在第一时钟信号（CLK_V“）的控制下输入由发送电路（302）发送的第一数据流的数据， 并且产生指示何时从第一数据缓冲器（336）读取数据值的信号触发信号，其中数据是从第一数据缓冲器（336）读取的，还是从耦合到第一数据缓冲器（336）的输出的另一数据缓冲器 在第二时钟信号（CLK R）的控制下，所述第一数据缓冲器（336）;以及信用生成电路（342），其被配置为基于所述信用触发信号来生成信用信号以用于向所述发送电路（302 ）在所述第一时钟信号（CLK_V“）的控制下，所述信用信号指示所述发送电路可以发送所述第一数据流的一个或多个其他数据值。

    TIME INTERLEAVER, TIME DEINTERLEAVER, TIME INTERLEAVING METHOD, AND TIME DEINTERLEAVING METHOD
    2.
    发明公开
    TIME INTERLEAVER, TIME DEINTERLEAVER, TIME INTERLEAVING METHOD, AND TIME DEINTERLEAVING METHOD 审中-公开
    时间交织器，时间去交织器，时间交织方法和时间去交织方法

    公开(公告)号：EP3203637A1

    公开(公告)日：2017-08-09

    申请号：EP15847888.3

    申请日：2015-09-10

    Applicant: Panasonic Corporation

    Inventor： KLENNER, Peter

    IPC: H03M13/27

    CPC classification number: H04L47/6245 ,  H03M13/27 ,  H03M13/271 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2785 ,  H03M13/2796 ,  H04L1/0071 ,  H04L1/0076 ,  H04L1/0085 ,  H04L47/6255

    Abstract: A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

    Abstract translation: 包括在执行卷积交织的时间交织器中的卷积交织器包括：第一开关，用于将卷积交织器的输入的连接目的地切换到多个分支中的一个的一端; 除了一个分支之外的多个分支中的一些分支中提供的FIFO存储器，其中多个FIFO存储器的数目在多个分支中是不同的; 以及第二开关，其将卷积交织器的输出的连接目的地切换到多个分支中的一个分支的另一端。 第一和第二开关通过在多个分支中顺序地和重复地切换连接目的地的对应分支而在与每帧的码字一样多的多个单元已经通过时切换连接目的地。

    RELAY DEVICE AND OUTPUT CONTROL METHOD
    3.
    发明公开
    RELAY DEVICE AND OUTPUT CONTROL METHOD 有权
    继电器件和输出控制方法

    公开(公告)号：EP2161888A1

    公开(公告)日：2010-03-10

    申请号：EP07743813.3

    申请日：2007-05-21

    Applicant: Fujitsu Limited

    Inventor： SHINOZAKI, Atsushi

    IPC: H04L13/08

    CPC classification number: H04L47/30 ,  H04L47/10 ,  H04L47/12 ,  H04L47/32 ,  H04L47/58 ,  H04L47/6245 ,  H04L49/90 ,  H04L49/9078

    Abstract: The continuation of the inability to reproduce data in a receiving apparatus is avoided.
    A buffer (1b) temporarily stores data received from a network (2a) by a receiving means (1a). An output mode switching means (1c) switches the mode in which the data received by the receiving means (1a) is output to the buffer (1b), between FIFO and FILO, in accordance with the storage amount of data temporarily stored in the buffer (1b). For example, if the data temporarily stored in the buffer (1b) falls below a given threshold value of the buffer (1b), data is stored in the buffer (1b) in FIFO. If the data temporarily stored in the buffer (1b) exceeds a given threshold value of the buffer (1b), data is stored in the buffer (1b) in FILO. A sending means (1d) outputs data taken from the buffer (1b) in FIFO or FILO, to a network (2b).

    Abstract translation: 避免了在接收装置中无法再现数据的延续。 缓冲器（1b）暂时存储由接收装置（1a）从网络（2a）接收的数据。 根据临时存储在缓冲器中的数据的存储量，输出模式切换装置（1c）将接收装置（1a）接收的数据输出到缓冲器（1b）的模式在FIFO和FILO之间切换 （1b）中。 例如，如果临时存储在缓冲器（1b）中的数据低于缓冲器（1b）的给定阈值，则将数据存储在FIFO中的缓冲器（1b）中。 如果临时存储在缓冲器（1b）中的数据超过缓冲器（1b）的给定阈值，则将数据存储在FILO中的缓冲器（1b）中。 发送装置（1d）将从FIFO或FILO中的缓冲器（1b）获取的数据输出到网络（2b）。

    DATA CACHING METHOD AND DEVICE, AND STORAGE MEDIUM
    5.
    发明公开
    DATA CACHING METHOD AND DEVICE, AND STORAGE MEDIUM 审中-公开
    数据缓存方法和装置以及存储介质

    公开(公告)号：EP3206123A1

    公开(公告)日：2017-08-16

    申请号：EP15850914.1

    申请日：2015-04-28

    Applicant: Sanechips Technology Co., Ltd.

    Inventor： ZHAO, Jiao ,  LAI, Mingliang ,  TIAN, Haoxuan ,  CHANG, Yanrui

    IPC: G06F5/08

    CPC classification number: H04L47/6245 ,  G06F12/0815 ,  G06F2212/1008 ,  G06F2212/154 ,  G06F2212/608 ,  H04L49/90

    Abstract: Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current K th cycle, scheduling for the cell to be dequeued to be dequeued, acquiring the actual value of the number of splicing units occupied by the cell to be dequeued, and storing the cell to be dequeued in a register the same number of bits wide as a bus in a cell splicing manner, wherein determining that the cell to be dequeued can be dequeued is conducted in accordance with the fact that a first back pressure count value of the (K-1) th cycle is less than or equal to a first preset threshold value, and the first back pressure count value of the (K-1) th cycle is obtained in accordance with an estimated value of the number of the splicing units occupied when the previous cell to be dequeued is dequeued, the number of splicing units capable of being transmitted by the bus in each cycle, and a first back pressure count value of the (K-2) th cycle. Also disclosed at the same time are a data caching device and a storage medium.

    Abstract translation: 公开了一种数据缓存方法，包括：根据小区的输入端口号，将所述小区存储在对应的先入先出队列中; 确定出现的小区可以在当前的第K个周期出队，调度出队的出队出队，获取待出队的小区占用的拼接单元数的实际值，并将该小区存储到 根据如下事实进行确定待出队的单元可以出队的步骤：在寄存器中以与单元接续方式的总线相同的比特数出队，其中，根据第（K- 1）周期小于或等于第一预设阈值，并且第（K-1）个循环的第一背压计数值根据当第（K-1）次循环时的拼接单元的数量的估计值来获得 先前要出队的单元出队，在每个循环中能够由总线传送的拼接单元的数量以及第（K-2）个循环的第一背压计数值。 同时还公开了一种数据缓存设备和一种存储介质。

    DATA PROCESSING APPARATUS, RECEPTION APPARATUS, DATA PROCESSING METHOD, AND PROGRAM
    6.
    发明公开
    DATA PROCESSING APPARATUS, RECEPTION APPARATUS, DATA PROCESSING METHOD, AND PROGRAM 审中-公开
    数据处理装置，接收装置，数据处理方法和程序

    公开(公告)号：EP3166322A1

    公开(公告)日：2017-05-10

    申请号：EP15815716.4

    申请日：2015-06-23

    Applicant: Sony Semiconductor Solutions Corporation

    Inventor： ISHII Michito

    IPC: H04N21/4385 ,  H04N21/434

    CPC classification number: H04L47/562 ,  H04L47/23 ,  H04L47/6245 ,  H04L69/22 ,  H04N21/434 ,  H04N21/4385 ,  H04W74/085

    Abstract: The present disclosure relates to a data processing device, a receiving device, a data processing method, and a program capable of suppressing degradation in quality in a case of reproducing data.
    Packet selection units select, from a multiplexed stream obtained by multiplexing a plurality of service streams, packets configuring respective service streams and generate one service stream. Insertion units insert null packets with time information, in which predetermined time information has been given to payloads, to spaces which have become empty when a predetermined number of the packet selection units generate the one service stream. Thereafter, in the streams which have been demultiplexed after being multiplexed, the timing to output the null packets with time information is adjusted with reference to the time information given to the null packets with time information. The present technology can be applied to, for example, a receiving device that can receive a plurality of streams.

    Abstract translation: 数据处理设备，接收设备，数据处理方法和程序技术领域本公开涉及能够在再现数据的情况下抑制质量下降的数据处理设备，接收设备，数据处理方法和程序。 分组选择单元从通过复用多个业务流获得的复用流中选择配置相应业务流的分组并且生成一个业务流。 当预定数量的分组选择单元产生一个业务流时，插入单元向空间中插入具有时间信息的空分组，其中将具有预定时间信息的时间信息提供给有效载荷。 此后，在多路复用后被解复用的流中，参照利用时间信息给出空分组的时间信息来调整输出具有时间信息的空分组的定时。 本技术可以应用于例如可以接收多个流的接收设备。

    ANNULAR OPTICAL BUFFER AND OPTICAL SIGNAL STORAGE AND READING METHOD
    7.
    发明公开
    ANNULAR OPTICAL BUFFER AND OPTICAL SIGNAL STORAGE AND READING METHOD 审中-公开
    环形光缓存和保存方法和光信号读

    公开(公告)号：EP3079311A4

    公开(公告)日：2016-12-21

    申请号：EP14876401

    申请日：2014-02-10

    Applicant: HUAWEI TECH CO LTD

    Inventor： SONG LIANG ,  YANG YINGCHUN ,  LIU YAODA

    IPC: H04L12/54 ,  G02B6/24 ,  H04L12/863 ,  H04Q11/00

    CPC classification number: H04Q11/0005 ,  H04L47/6245 ,  H04Q11/0003 ,  H04Q2011/0016 ,  H04Q2011/002 ,  H04Q2011/0033 ,  H04Q2011/0039 ,  H04Q2213/003

    Abstract: An annular optical buffer (100) and methods for storing and reading an optical signal are disclosed. The optical buffer (100) includes: a first bent straight-through waveguide (101a), functioning as a transmission bus of an optical signal; multiple optical delay waveguide loops (103), configured to temporarily store optical signals; multiple pairs of optical switches (102), whose quantity is the same as that of the multiple optical delay waveguide loops (103), where each pair of optical switches (102) are configured to control on and off of an optical paththat is ontwo arms of the first bent straight-through waveguide (101a) and two sides of an optical delay waveguide loop (103) corresponding to each pair of optical switches (102); a beamsplitter (106), configured to obtain a part of optical signal by splitting the optical signal that is input from an input end and transfer the part of optical signal to a controller (105) through a second bent straight-through waveguide (101c); a slow light effect waveguide (104a), configured to slow a transmission rate of an optical signal transmitted within the slow light effect waveguide; and the controller (105), configured to control storage and read of the optical signal. By means of the foregoing annular optical buffer (100), monolithic integration of an optical buffer and unordered random storage and reading of an optical signal can be implemented.

    DATA BUFFERING SYSTEM AND METHOD FOR ETHERNET DEVICE
    9.
    发明公开
    DATA BUFFERING SYSTEM AND METHOD FOR ETHERNET DEVICE 有权
    数据缓冲系统和方法以太网设备

    公开(公告)号：EP2913963A4

    公开(公告)日：2015-10-28

    申请号：EP13849347

    申请日：2013-10-21

    Applicant: ZTE CORP

    Inventor： YUAN FENG

    IPC: H04L12/70 ,  H04L12/879 ,  H04L12/931

    CPC classification number: H04L49/351 ,  H04L47/6245 ,  H04L49/901 ,  H04L61/6009

    Abstract: A data caching method for an Ethernet device is provided. The method includes: receiving data frames from various Ethernet interfaces and converting the Ethernet data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; maintaining a cache address in which data has already been written and a currently idle cache address in a cache; receiving the currently idle cache address and generating a write instruction and/or a read instruction for the cache and performing a write operation and/or a read operation so as to write the data received and processed by an IPC into the currently idle cache or to read data from the cache; and performing bit conversion and format encapsulation on the data that is read according to a read request and outputting the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface. A data caching system for an Ethernet device is also provided. By means of the data caching method and system provided herein, the expandability and the high bandwidth storage capacity of a network switching device can be improved, a high bandwidth utilization rate is achieved, and it becomes possible to improve bandwidth utilization rate based on traffic management.

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