摘要:
A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.
摘要:
The invention relates to a method for transmitting an actuation signal (3) and a first data signal (4) between a control device (9) and an actuation device (12) of a power semiconductor device (13). In order to minimize the expenditure for the operation of the physical transmission channels and the costs for the laying of the physical connection between control device (9) and actuation device (12), it is proposed that the transmission of the actuation signal (3) and the first data signal (4) between the control device (9) and the actuation device (12) takes place simultaneously and via a common transmission channel, the first data signal (4) being combined with the actuation signal (3) by means of a digital modulation method or coding method.
摘要:
A circuit arrangement which is designed to output a voltage pulse on a bus line has a device which is designed to determine whether a voltage on the bus line has reached a specified threshold value.
摘要:
Electronic communication system, comprising at least one first and one second communication unit (1, 2) connected together by way of at least one first data line (3), wherein the communication system comprises a data transfer protocol according to which the first communication unit (1) transfers a data request signal or clock signal at least once over the first data line (3) to the second communication unit (2) in at least one first data transmission mode for synchronous data transmission and wherein the second communication unit (2) transfers a data signal as an answer to the data request signal or the clock signal over the first data line (3) to the first communication unit (1).
摘要:
A method of synchronising data in a communications system (10) comprises the steps of: (a) Generating at transmitting means (20) a composite signal comprising a serial stream of data partitioned in one or more frames; (b) transmitting the composite signal through communicating means (50) to receiving means (30); (c) generating multiphase clock signals; (d) comparing the composite signal received at the receiving means with each of the multiphase clock signals until either sustained coincidence therebetween is achieved or sustained non-coincidence is achieved, thereby synchronising the receiving means to bit boundaries in the composite signal and to one or more of the clock phase signals; (e) correlating one or more bit templates at the receiving means with one or more corresponding bit templates in the composite signal received at the receiving means to determine where frames start in the composite signal, thereby synchronising the receiving means to the one or more frames in the composite signal.
摘要:
Systems and methods provide for data transfer and transmission according to a synchronous one-bit interface protocol. A bit stream is generated including first data to be transferred or transmitted and second data from which a clock period used to encode the first data may be extracted. The bit stream is provided to a processor for decoding. In one embodiment, the bit stream includes a start segment or sequence, a data segment and a stop segment or sequence. A clock period is encoded into and is extracted from the start and/or stop sequences. The data segment is decoded on the basis of the clock period.
摘要:
A real-time clock (151) for electronic equipment is synchronized by supplying a time signal (4-1) to a serial communications circuit (11) with the data transmission rate adapted so that one character of the time signal can be read into the serial communications circuit as one character. The serial communications circuit (11) initiates (4-2) an interrupt handler (131) that in turn initiates (4-7) a sync task (132) . The time signal (4-1) is inverted if necessary before being supplied to the serial communications circuit (11) . In this way the time signal is superimposed over the serial data.