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    RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREFOR
    3.
    发明公开
    RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREFOR 审中-实审

    公开(公告)号：EP4418844A1

    公开(公告)日：2024-08-21

    申请号：EP21968508.8

    申请日：2021-12-21

    申请人： Huawei Technologies Co., Ltd.

    发明人： LIU, Xixia ,  ZHOU, Xue ,  WANG, Xiaojie ,  QIN, Qing ,  JIAO, Huifang

    IPC分类号： H10N70/00

    CPC分类号： H10N70/826 ,  H10N70/8418 ,  H10N70/011 ,  H10N70/8833 ,  H10N70/24 ,  H10N70/245 ,  H10B63/82 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/883

    摘要： This disclosure relates to a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a first electrode layer, a second electrode layer, and a resistive dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer, the second electrode layer, and the resistive dielectric layer are of a sandwich structure. The second electrode layer includes a plurality of through holes, and the plurality of through holes are filled with electrode materials. This may form an annular electrode or a sawtooth electrode. Because an electrode with a target size is disposed at a target position, second electrodes are regular, even, and flat, and have a relatively small conductive filament forming area, so that a current providing position can be effectively controlled, and a position for generating a metal cation or an oxygen defect vacancy can be controlled to a maximum extent. In this way, generation randomness of a conductive filament is reduced, and shape uniformity of the conductive filament is improved, thereby improving performance consistency in resistive random access memories, for example, consistency of D2D and C2C.

    ANALOG PROGRAMMABLE RESISTIVE MEMORY
    5.
    发明公开
    ANALOG PROGRAMMABLE RESISTIVE MEMORY 审中-公开

    公开(公告)号：EP4358687A1

    公开(公告)日：2024-04-24

    申请号：EP23202286.3

    申请日：2023-10-07

    申请人： Cyberswarm, Inc

    发明人： DUMITRU, Viorel-Georgel ,  IONESCU, Octavian-Narcis

    IPC分类号： H10N70/00 ,  G11C11/56 ,  H10N70/20

    CPC分类号： H10N70/026 ,  H10N70/011 ,  H10N70/20 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8836 ,  G11C11/5685 ,  H10N70/8418

    摘要： One or more embodiments disclosed herein describe a nonvolatile, analog programmable resistive memory with a plurality of memory states. The programmable resistive memory includes a substrate, an IGZO resistive layer and electrical contacts. The electrical contacts are deposited on the IGZO layer, in the same plane. The electrical contacts may have various shapes in order to obtain spatially variable distances between the electrical contacts. The resistance of the resistive memory can be brought from an initial low value to a plurality of various higher values by applying electrical voltage pulses with various durations and various amplitudes and/or by applying one or more DC voltage sweeps. Also, the high voltage limit during the DC voltage sweeps could be set at values ranging from few volts to few tens of volts. In this manner, the IGZO programmable resistive memory could be set in a plurality of memory states.