公开(公告)号：EP3336895A2

公开(公告)日：2018-06-20

申请号：EP17207632.5

申请日：2017-12-15

Applicant: Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

Inventor： ZHOU, Ming

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L27/0207 ,  C01B21/0828 ,  C07F7/0803 ,  H01L21/02074 ,  H01L21/0212 ,  H01L21/31127 ,  H01L21/76811 ,  H01L21/76829 ,  H01L23/528 ,  H01L23/53295

Abstract: A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a dielectric layer (202) on the metal interconnect layer, forming a fluorocarbon layer (301) on the dielectric layer, forming a patterned hardmask layer on the fluorocarbon layer, etching the fluorocarbon layer and the dielectric layer using the patterned hardmask layer as a mask to form a trench in the dielectric layer and a through-hole through the dielectric layer to the metal interconnect layer, forming a metal layer filling the trench and the through-hole, and planarizing the metal layer until the planarized metal layer (801) has an upper surface that is flush with an upper surface of the fluorocarbon layer. The interconnect structure thus formed has an improved reliability.

公开(公告)号：EP3304592A1

公开(公告)日：2018-04-11

申请号：EP16730939.2

申请日：2016-05-31

Applicant: Raytheon Company

Inventor： LAROCHE, Jeffrey R. ,  BETTENCOURT, John P. ,  KAZIOR, Thomas E. ,  IP, Kelly P.

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/66 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2223/6627 ,  H01L2223/6683

Abstract: A semiconductor structure having a semiconductor layer having an active device therein. A dielectric structure is disposed over the semiconductor layer, such dielectric structure having open ended trench therein. An electrical interconnect level is disposed in the trench and electrically connected to the active device. A plurality of stacked metal layers is disposed in the trench. The stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.

公开(公告)号：EP3133637B1

公开(公告)日：2018-04-11

申请号：EP16191043.5

申请日：2005-10-04

Applicant: Fujitsu Semiconductor Limited

Inventor： KOURA, Yumiko ,  KITADA, Hideki ,  OZAWA, Kiyoshi

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To manufacture a semiconductor device with copper plugs and/or wirings, the following steps are performed. (a) A copper alloy film (16, 17) containing at least two metallic elements in addition to copper is formed on the surface of an insulator (15) containing oxygen and formed on a semiconductor substrate (1). (b) A metal film (18) made of pure copper or copper alloy is formed on the copper alloy film (16, 17). (c) After step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator (15) and the metallic elements in the copper alloy film (16, 17).

公开(公告)号：EP3301705A1

公开(公告)日：2018-04-04

申请号：EP17192406.1

申请日：2017-09-21

Applicant: Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

Inventor： ZHOU, Ming

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/31122 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295

Abstract: A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a first dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the first dielectric layer, forming a second dielectric layer on the fluorocarbon layer, and performing an etch process on the second dielectric layer using the fluorocarbon layer as an etch stop mask to form an opening. The interconnect structure thus formed has an improved uniformity and reduced parasitic capacitance.

Abstract translation: 用于制造互连结构的方法包括：提供金属互连层;在金属互连层上形成第一电介质层;在第一电介质层上形成氟碳层;在氟碳层上形成第二电介质层;以及执行蚀刻工艺 在第二电介质层上使用氟碳化合物层作为蚀刻停止掩模以形成开口。 这样形成的互连结构具有改善的均匀性和降低的寄生电容。

公开(公告)号：EP3289608A1

公开(公告)日：2018-03-07

申请号：EP15890917.6

申请日：2015-04-29

Applicant: Intel Corporation

Inventor： CHAWLA, Jasmeet S. ,  HOURANI, Rami ,  KOBRINSKY, Mauro J. ,  GSTREIN, Florian ,  CLENDENNING, Scott B. ,  ROBERTS, Jeanette M.

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2221/101 ,  H01L2221/1063

Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

公开(公告)号：EP3050085A4

公开(公告)日：2017-05-24

申请号：EP13894130

申请日：2013-09-27

Applicant: INTEL CORP

Inventor： WALLACE CHARLES H ,  NYHUS PAUL A

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/764 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

Abstract translation: 描述了用于后端线路（BEOL）互连的自对准通孔和插头图案化。 在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和电介质线的光栅。 互连结构的第二层设置在第一层上方。 第二层包括在垂直于第一方向的第二方向上交替的金属线和电介质线的光栅。 第二层的光栅的每条金属线设置在具有与互连结构的第一层的交替金属线和电介质线对应的第一电介质材料和第二电介质材料的交替不同区域的凹陷电介质线上。 第二结构的光栅的每个电介质线具有不同于第一电介质材料和第二电介质材料的交替不同区域的第三电介质材料的连续区域。

公开(公告)号：EP3116022A3

公开(公告)日：2017-03-08

申请号：EP16175260.5

申请日：2016-06-20

Applicant: IMEC VZW

Inventor： DE WOLF, Ingrid ,  BÖMMELS, Jürgen

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76825 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76877 ,  H01L23/53295 ,  H01L24/02 ,  H01L2224/02372

Abstract: The present invention is related to a method for producing an integrated circuit device, comprising a Front-end-of-line (FEOL) portion and a Back-end-of-line (BEOL) portion (102). The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within said dielectric layers. In a device according to the invention, in at least some of the metallization layers of the BEOL stack, the elastic modulus of the dielectric material varies from one area of the layer to one or more other areas of the layer. In the method of the invention, a mask layer (21) is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, said mask layer covering portions of the stack area and exposing other portions of said area. Then a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in the areas not covered by the mask layer.

Abstract translation: 本发明涉及一种用于制造集成电路器件的方法，所述集成电路器件包括前线工序（FEOL）部分和后工序后工序（BEOL）部分（102）。 金属化层包括介电层，优选低k介电层，其中金属导体和/或互连结构结合在所述介电层内。 在根据本发明的装置中，在BEOL堆叠的至少一些金属化层中，介电材料的弹性模量从该层的一个区域到该层的一个或多个其他区域而变化。 在本发明的方法中，在堆叠的制造期间，在BEOL堆叠上或在其中一个金属化层上施加掩模层（21），所述掩模层覆盖堆叠区域的一部分并暴露所述区域的其他部分。 然后进行处理，其改变一个或多个金属化层中的电介质材料的弹性模量，但仅在未被掩模层覆盖的区域中。

公开(公告)号：EP3082161A1

公开(公告)日：2016-10-19

申请号：EP16165360.5

申请日：2016-04-14

Applicant: Freescale Semiconductor, Inc.

Inventor： Reber, Douglas ,  Shroff, Mehul

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/7688 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/53295

Abstract: A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor (304) and the second conductor (306), removing patterned material to form an air gap (402) between the first conductor and the second conductor, applying a self-supporting film (404), preferably graphene or silicene, on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 制造半导体器件的方法可以包括图案化用于第一导体和第二导体的层，电镀图案化部分的层以形成第一导体（304）和第二导体（306），去除图案化材料以形成空气 在第一导体和第二导体之间的间隙（402），在第一导体和第二导体的顶部上施加自支撑膜（404），优选石墨烯或硅，以封闭气隙，并使自支撑 导致自支撑膜基本上不导电的膜。

公开(公告)号：EP3050084A1

公开(公告)日：2016-08-03

申请号：EP13894765.0

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

IPC: H01L21/31

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

公开(公告)号：EP2615635B1

公开(公告)日：2016-05-25

申请号：EP11823646.2

申请日：2011-09-08

Applicant: Mitsui Chemicals, Inc.

Inventor： ONO, Shoko ,  KOHMURA, Kazuo ,  TANAKA, Hirofumi

IPC: H01L21/312 ,  C09K3/10 ,  H01L21/304 ,  H01L21/308 ,  H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/02334 ,  C09K3/1006 ,  C09K2200/0645 ,  H01L21/02063 ,  H01L21/02087 ,  H01L21/0209 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00