公开(公告)号：EP1405347A4

公开(公告)日：2009-08-19

申请号：EP02794642

申请日：2002-07-11

申请人： GEN SEMICONDUCTOR INC

发明人： EINTHOVEN WILLEM G ,  GINTY ANTHONY ,  WALSH AIDAN

IPC分类号： H01L29/861 ,  H01L21/329 ,  H01L27/02 ,  H01L27/108 ,  H01L29/06

CPC分类号： H01L29/0607 ,  H01L27/0259 ,  H01L29/66121 ,  H01L29/8618 ,  Y10S438/912 ,  Y10S438/965

摘要： A bi-directional transient voltage suppression device is provided. The device comprises: lower semiconductor layer of p+type conductivity (14); upper semiconductor layer of p+type conductivity (18); middle semiconductor layer of n type conductivity (16) adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; mesa trench (23) extending through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and an oxide layer (19) covering at least portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer (16) doping concentration of this device, when taken over the distance between the junctions. A method of making such a device is also provided, which comprises: providing a p+type semiconductor substrate (12); epitaxially depositing a lower semiconductor layer of p+type conductivity (14); epitaxially depositing a middle semiconductor layer of n type conductivity (16) over the lower layer; epitaxially depositing an upper semiconductor layer of p+type conductivity (18) over the middle layer (16); heating the substrate (12), the lower epitaxial layer (14), the middle epitaxial layer (16) and the upper epitaxial layer (18); etching the mesa trench (23) that extends through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and thermally growing an oxide layer (19) on at least those portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions of the device.

公开(公告)号：EP1405347A2

公开(公告)日：2004-04-07

申请号：EP02794642.5

申请日：2002-07-11

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： EINTHOVEN, Willem, G. ,  GINTY, Anthony ,  WALSH, Aidan

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/00 ,  H01L23/62

CPC分类号： H01L29/0607 ,  H01L27/0259 ,  H01L29/66121 ,  H01L29/8618 ,  Y10S438/912 ,  Y10S438/965

摘要： A bi-directional transient voltage suppression device is provided. The device comprises: lower semiconductor layer of p+type conductivity (14); upper semiconductor layer of p+type conductivity (18); middle semiconductor layer of n type conductivity (16) adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; mesa trench (23) extending through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and an oxide layer (19) covering at least portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer (16) doping concentration of this device, when taken over the distance between the junctions. A method of making such a device is also provided, which comprises: providing a p+type semiconductor substrate (12); epitaxially depositing a lower semiconductor layer of p+type conductivity (14); epitaxially depositing a middle semiconductor layer of n type conductivity (16) over the lower layer; epitaxially depositing an upper semiconductor layer of p+type conductivity (18) over the middle layer (16); heating the substrate (12), the lower epitaxial layer (14), the middle epitaxial layer (16) and the upper epitaxial layer (18); etching the mesa trench (23) that extends through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and thermally growing an oxide layer (19) on at least those portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions of the device.