公开(公告)号：EP1451877A4

公开(公告)日：2009-06-03

申请号：EP02786713

申请日：2002-11-13

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/513 ,  H01L29/7813

摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

公开(公告)号：EP1476894A4

公开(公告)日：2009-02-18

申请号：EP02794456

申请日：2002-12-30

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/22 ,  H01L21/225 ,  H01L21/329 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

公开(公告)号：EP1454361A4

公开(公告)日：2009-01-21

申请号：EP02803696

申请日：2002-11-20

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-LUAN ,  SO KOON CHONG ,  AMATO JOHN E ,  TSUI YAN MAN

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/456

摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

公开(公告)号：EP1454360A4

公开(公告)日：2008-12-17

申请号：EP02782334

申请日：2002-11-20

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG ,  AMATO JOHN E ,  TSUI YAN MAN

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L29/36

CPC分类号： H01L29/0878 ,  H01L29/7813

摘要： A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent the insulating layer and forming a source region of said first conductivity type within an upper portion of the body region and adjacent the trench.

公开(公告)号：EP1446839A4

公开(公告)日：2008-12-10

申请号：EP02789331

申请日：2002-10-30

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-LUAN ,  SO KOON CHONG ,  NELSON WILLIAM JOHN ,  AMATO JOHN E

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811

摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

公开(公告)号：EP1405347A4

公开(公告)日：2009-08-19

申请号：EP02794642

申请日：2002-07-11

申请人： GEN SEMICONDUCTOR INC

发明人： EINTHOVEN WILLEM G ,  GINTY ANTHONY ,  WALSH AIDAN

IPC分类号： H01L29/861 ,  H01L21/329 ,  H01L27/02 ,  H01L27/108 ,  H01L29/06

CPC分类号： H01L29/0607 ,  H01L27/0259 ,  H01L29/66121 ,  H01L29/8618 ,  Y10S438/912 ,  Y10S438/965

摘要： A bi-directional transient voltage suppression device is provided. The device comprises: lower semiconductor layer of p+type conductivity (14); upper semiconductor layer of p+type conductivity (18); middle semiconductor layer of n type conductivity (16) adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; mesa trench (23) extending through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and an oxide layer (19) covering at least portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer (16) doping concentration of this device, when taken over the distance between the junctions. A method of making such a device is also provided, which comprises: providing a p+type semiconductor substrate (12); epitaxially depositing a lower semiconductor layer of p+type conductivity (14); epitaxially depositing a middle semiconductor layer of n type conductivity (16) over the lower layer; epitaxially depositing an upper semiconductor layer of p+type conductivity (18) over the middle layer (16); heating the substrate (12), the lower epitaxial layer (14), the middle epitaxial layer (16) and the upper epitaxial layer (18); etching the mesa trench (23) that extends through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and thermally growing an oxide layer (19) on at least those portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions of the device.

公开(公告)号：EP1393379A4

公开(公告)日：2009-08-12

申请号：EP02739587

申请日：2002-05-31

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG

IPC分类号： H01L29/872 ,  H01L21/329 ,  H01L27/08 ,  H01L27/095 ,  H01L29/417 ,  H01L29/47

CPC分类号： H01L29/417 ,  H01L27/0817 ,  H01L27/095 ,  H01L29/42364 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/8725

摘要： a schottky rectifier is provided. The Schottky rectifier comprises: (A) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region (12C) of first conductivity type adjacent the first face (12A) and a drift region(12D) of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (B) one or more trenches extending from the second face (12B) into the semiconductor region and defining one or more mesas (14) within the semiconductor region; (C) an insulating region (16) adjacent the semiconductor region in lower portions of the trench; (D) and an anode electrode (18) that is (I) adjacent to and forms a schottky rectifying contact with the semiconductor at the second face (12), (II) adjacent to and forms a schottky rectifying contact with the semiconductor region within upper portions of the trench and (III) adjacent to the insulating region (16) within the lower portions of the trench.

摘要翻译： 提供肖特基整流器。 肖特基整流器包括：（A）具有第一和第二相对面的半导体区域，其中半导体区域包括与第一面（12A）相邻的第一导电类型的阴极区域（12C）和第一导电类型的第一漂移区域 所述漂移区具有比所述阴极区域的净掺杂浓度低的导电类型，并且所述漂移区域具有比所述阴极区域低的净掺杂浓度; （B）从所述第二面（12B）延伸到所述半导体区域中并且在所述半导体区域内限定一个或多个台面（14）的一个或多个沟槽; （C）在所述沟槽的下部中与所述半导体区域相邻的绝缘区域（16）; （D）和阳极电极（18），所述阳极电极（18）在所述第二面（12）处与所述半导体相邻且与所述半导体形成肖特基整流接触，所述第二面与所述半导体区域相邻且与所述半导体区域形成肖特基整流接触 沟槽的上部和（III）与沟槽的下部内的绝缘区域（16）相邻。

公开(公告)号：EP1476895A4

公开(公告)日：2009-07-15

申请号：EP03716108

申请日：2003-02-20

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L29/66712 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/7802

摘要： A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a thin oxide layer and a polycrystalline semiconductor material (e.g., polysilicon) that includes a dopant of the second conductivity type. The thin oxide layer is dissolved into the epitaxial layer, dopant is diffused from the trenches into portions of the epitaxial layer adjacent to the trenches, and the polycrystalline semiconductor material is converted to a single crystal material, thus forming the p-type doped regions that cause the reverse voltage to be built up in the horizontal direction as well as the vertical direction.

摘要翻译： 提供功率MOSFET，其包括第一导电类型的衬底。 在衬底上沉积也具有第一导电类型的外延层。 第一和第二体区位于外延层中并且在它们之间限定漂移区。 身体区域具有第二导电类型。 第一导电类型的第一和第二源极区域分别位于第一和第二体区域中。 多个沟槽位于外延层的漂移区域的主体区域的下方。 从第一和第二体区向衬底延伸的沟槽填充有薄氧化物层和包括第二导电类型的掺杂剂的多晶半导体材料（例如多晶硅）。 将薄氧化物层溶解到外延层中，掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分，并且多晶半导体材料被转换为单晶材料，从而形成p型掺杂区域， 导致在水平方向和垂直方向上建立反向电压。

公开(公告)号：EP1433200A4

公开(公告)日：2009-03-11

申请号：EP02784020

申请日：2002-10-03

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A ,  GUILLOT JEAN-MICHEL

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L29/66712 ,  H01L29/7802

摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

公开(公告)号：EP1468452A4

公开(公告)日：2009-01-07

申请号：EP02799348

申请日：2002-12-30

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/329 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer. A second doped layer is formed in the same manner as the first doped layer. The second doped layer is located vertically below the first doped layer. A filler material is deposited in the trench to substantially fill the trench. The dopant in the first and second doped layers are diffused to cause the first and second doped layers to overlap one another, thus completing the voltage sustaining region. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.