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    HIGH THROUGHPUT POLAR CODEWORD DECODING BY DECODING BCH SUB-CODE IN POLAR CODE STRUCTURE
    1.
    发明公开
    HIGH THROUGHPUT POLAR CODEWORD DECODING BY DECODING BCH SUB-CODE IN POLAR CODE STRUCTURE 审中-公开

    公开(公告)号：EP4462434A1

    公开(公告)日：2024-11-13

    申请号：EP24166781.5

    申请日：2024-03-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： BERMAN, Amit ,  SHAPIRO, Dikla ,  DEKEL, Idan

    IPC分类号： G11C29/52 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G11C29/04 ,  H03M13/15

    摘要： Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a frame corresponding to a codeword from the storage device, performing a first decoding operation on the frame, based on the first decoding operation indicating that a number of errors is greater than a predetermined number, selecting at least one potential error bit, and perform a second decoding operation based on the at least one potential error bit, based on the second decoding operation indicating that the number of errors is not equal to the predetermined number plus one, determining that the frame is not correctable by the first decoding operation and the second decoding operation, and based on the second decoding operation indicating that the number of errors is equal to the predetermined number plus one, correcting the frame based on a result of the second decoding operation to obtain a corrected frame, and obtaining information bits corresponding to the codeword based on the corrected frame.

    COMPUTING SYSTEM AND METHOD OF OPERATION THEREOF
    2.
    发明公开
    COMPUTING SYSTEM AND METHOD OF OPERATION THEREOF 审中-公开

    公开(公告)号：EP4462433A1

    公开(公告)日：2024-11-13

    申请号：EP23179610.3

    申请日：2023-06-15

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： TSENG, Po-Hao ,  LEE, Ming-Hsiu ,  BO, Tian-Cih

    IPC分类号： G11C15/04 ,  G11C16/04 ,  G06F7/74

    摘要： A 3D search engine receives searches for application to word lines of a nonvolatile memory array. The engine uses two word lines per bit of information of the searches and two memory devices per bit of stored feature to search against, optionally enabling don't care and/or wildcard encoding. The engine uses respective bit lines of the nonvolatile memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the nonvolatile memory array are usable to store respective data words, e.g., corresponding to features to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. Various encodings of features and searches enable exact, approximate, and range matching. The engine has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

    MEMORY ACCESS LATENCY ESTIMATION METHOD AND MEMORY ACCESS LATENCY ESTIMATION SYSTEM FOR ESTIMATING AN ACCESS LATENCY OF A MEMORY ACCORDING TO A PLURALITY OF COEFFICIENTS AND A PLURALITY OF INDEXES
    6.
    发明公开
    MEMORY ACCESS LATENCY ESTIMATION METHOD AND MEMORY ACCESS LATENCY ESTIMATION SYSTEM FOR ESTIMATING AN ACCESS LATENCY OF A MEMORY ACCORDING TO A PLURALITY OF COEFFICIENTS AND A PLURALITY OF INDEXES 审中-公开

    公开(公告)号：EP4456072A2

    公开(公告)日：2024-10-30

    申请号：EP24172130.7

    申请日：2024-04-24

    申请人： MediaTek Inc.

    发明人： CHANG, Chih-Chieh ,  SUN, You-Hong ,  LIN, Wen-Hsun ,  CHANG, Chia-Ching

    IPC分类号： G11C29/02

    摘要： A memory access latency estimation method includes measuring a first access latency of a first access operation of a first memory (310), measuring a plurality of first indexes of the first memory corresponding to the first access operation (320), using a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency (330), adjusting the plurality of first coefficients to generate a plurality of updated first coefficients (340), using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency (350), and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation (360).

    MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME
    7.
    发明公开
    MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：EP4456069A1

    公开(公告)日：2024-10-30

    申请号：EP23208292.5

    申请日：2023-11-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： YANG, Yunseok ,  JEONG, Yunkyeong ,  SHIN, Jaewoo ,  AN, Minhwan ,  CHUNG, Jin Suk

    IPC分类号： G11C5/04 ,  G11C7/10 ,  G11C11/4093

    摘要： A memory device (110) includes a first physical interface (111), a second physical interface (112), a first memory core (113), a second memory core (114), and a setting circuit. The first memory core (113) is assigned to the first physical interface (111) and includes a plurality of first stacked memory dies (431 to 438) and connected via a through electrode. The second memory core (114) is assigned to the second physical interface (112) and includes a plurality of second stacked memory dies (441 to 448) connected via a through electrode. The setting circuit sets at least one physical interface to be used for connection with an external device (120) of the memory device (110) among the first physical interface (111) and the second physical interface (112).