公开(公告)号：EP3992973A1

公开(公告)日：2022-05-04

申请号：EP21193306.4

申请日：2016-08-04

Applicant: Intel Corporation

Inventor： HALBERT, John B. ,  BAINS, Kuljit S.

IPC: G11C29/52 ,  G11C11/409 ,  G06F11/10 ,  G11C29/42

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

公开(公告)号：EP3712893A1

公开(公告)日：2020-09-23

申请号：EP20166515.5

申请日：2016-05-27

Applicant: INTEL Corporation

Inventor： HALBERT, John B. ,  BAINS, Kuljit S.

IPC: G11C29/42 ,  G11C29/52 ,  G06F11/10 ,  G11C29/44

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

公开(公告)号：EP3423945A1

公开(公告)日：2019-01-09

申请号：EP17763682.6

申请日：2017-01-16

Applicant: Intel Corporation

Inventor： VERGIS, George ,  BAINS, Kuljit S. ,  NALE, Bill

IPC: G06F12/02

公开(公告)号：EP3423932A1

公开(公告)日：2019-01-09

申请号：EP17760425.3

申请日：2017-01-16

Applicant: Intel Corporation

Inventor： COX, Christopher E. ,  BAINS, Kuljit S. ,  MCCALL, James A.

IPC: G06F3/06

公开(公告)号：EP2619763B1

公开(公告)日：2018-08-22

申请号：EP11827743.3

申请日：2011-09-26

Applicant: Intel Corporation

Inventor： BAINS, Kuljit S.

IPC: G11C11/401 ,  G11C11/4063 ,  G06F12/00 ,  G11C11/406 ,  G06F13/16 ,  G11C7/04

CPC classification number: G11C11/40618 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40622

Abstract: Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device.

公开(公告)号：EP3324411A1

公开(公告)日：2018-05-23

申请号：EP18150048.9

申请日：2011-06-27

Applicant: INTEL Corporation

Inventor： MCCALL, James ,  BAINS, Kuljit S.

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4093 ,  G06F13/40

CPC classification number: G11C7/1045 ,  G06F13/4086 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

公开(公告)号：EP2035938B1

公开(公告)日：2012-02-15

申请号：EP07799113.1

申请日：2007-06-27

Applicant: Intel Corporation

Inventor： BAINS, Kuljit S.

IPC: G06F12/16 ,  G11C29/00

CPC classification number: G06F11/1008

Abstract: Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

公开(公告)号：EP4109271A2

公开(公告)日：2022-12-28

申请号：EP22163660.8

申请日：2022-03-22

Applicant: INTEL Corporation

Inventor： NALE, Bill ,  BAINS, Kuljit S. ,  BLANKENBECKLER, Lawrence ,  ANDERSON, Ronald ,  LEE, Jongwon

IPC: G06F11/10

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

公开(公告)号：EP3657506A1

公开(公告)日：2020-05-27

申请号：EP19211469.2

申请日：2016-03-07

Applicant: INTEL Corporation

Inventor： MCCALL, James A. ,  BAINS, Kuljit S.

IPC: G11C29/02 ,  G11C29/46 ,  G11C7/06 ,  G11C7/04 ,  G11C7/10 ,  G06F11/30 ,  G06F13/42

Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

公开(公告)号：EP3314446A1

公开(公告)日：2018-05-02

申请号：EP16814998.7

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： TOMISHIMA, Shigeki ,  LU, Shih-Lien ,  BAINS, Kuljit S.

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G11C7/08 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/409

Abstract: A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.