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1.发明公开
公开(公告)号：EP4379721A1
公开(公告)日：2024-06-05
申请号：EP23199513.5
申请日：2023-09-25
发明人： KIM, Chinam , KO, Tae-Kyeong , KIM, Cholmin
CPC分类号： G11C8/12 , G11C11/4087 , G11C8/10 , G11C7/1072 , G06F12/0223 , G06F13/1631
摘要： A semiconductor memory system includes a memory device including plural banks, and a memory controller that generates an offset address for a first bank among the plural banks and a command indicating the offset address, based on a first request. The memory device generates a first address by adding the offset address to a base address for the first bank, according to the command, and performs a memory operation on the first address of the first bank according to the command.
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公开(公告)号：EP3769307B1
公开(公告)日：2023-11-08
申请号：EP19771178.1
申请日：2019-01-28
发明人： TIWARI, Vipin , TRAN, Hieu, Van , DO, Nhan , REITEN, Mark
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公开(公告)号：EP4014107A1
公开(公告)日：2022-06-22
申请号：EP20852170.8
申请日：2020-07-01
发明人： MURPHY, Richard C. , HUSH, Glen E. , SUN, Honglin
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公开(公告)号：EP3937173A1
公开(公告)日：2022-01-12
申请号：EP21184730.6
申请日：2021-07-09
发明人： JAIN, Sanjeev Kumar
摘要： Systems and method are provided for a memory circuit. A predecoder circuit is configured to receive a first address signal, a first clock signal, and a second clock signal. The predecoder circuit is configured to generate a selection signal based on the first clock signal and the first address signal. And the predecoder circuit is further configured to maintain the selection signal based on the second clock signal and the first address signal.
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公开(公告)号：EP3888087A1
公开(公告)日：2021-10-06
申请号：EP19889637.5
申请日：2019-11-20
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公开(公告)号：EP3692533A1
公开(公告)日：2020-08-12
申请号：EP18864883.6
申请日：2018-09-28
发明人： KIM, Kang-Yong , LEE, Hyun Yoo , PORTER, John D.
IPC分类号： G11C7/22 , G11C8/10 , G06F12/0831
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公开(公告)号：EP3660901A1
公开(公告)日：2020-06-03
申请号：EP20152687.8
申请日：2016-12-19
发明人： OGAWA, Hiroyuki , TOYAMA, Fumiaki , ARIKI, Takuya
IPC分类号： H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11565 , H01L27/11575 , H01L27/11582 , G11C5/02 , G11C8/10 , G11C16/04 , G11C16/08
摘要： The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
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10.发明公开
公开(公告)号：EP3651155A1
公开(公告)日：2020-05-13
申请号：EP19195249.8
申请日：2019-09-03
发明人： KIM, Dae-Jin , PARK, Sang-Ryong , BAEK, Jong-Nam , JANG, Sejeong
IPC分类号： G11C16/34 , G11C16/08 , G11C16/10 , G11C11/56 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/16 , G11C5/02 , G11C11/16 , G11C11/22 , G11C13/00 , G06F12/02
摘要： A nonvolatile memory device includes a memory cell array that includes memory blocks, wherein each of the memory blocks includes pages each including memory cells, a row decoder circuit that selects one of the pages from a selected memory block of the memory blocks in a write operation and selects memory cells of a close unit from the selected memory block in a close operation, and a page buffer circuit that writes data into memory cells of a page selected by the row decoder circuit in the write operation and writes dummy data into the memory cells of the close unit selected by the row decoder circuit in the close operation. The close unit includes one or more pages, and, in the close operation, the row decoder circuit adjusts a size of the close unit.
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