公开(公告)号：EP0077567A3

公开(公告)日：1984-05-09

申请号：EP82109642

申请日：1982-10-19

申请人： Hitachi, Ltd.

发明人： Ito, Shigeyuki ,  Watatani, Yoshizumi ,  Owashi, Hitoaki

IPC分类号： H03C03/00 ,  H03D03/24 ,  H04N05/92

CPC分类号： H03D3/241 ,  H03C3/00 ,  H04N9/802

摘要： modulator-demodulator suited to record an audio signal in a recording medium in the form of a frequency-modulated signal and to demodulate the frequency-modulated signal is disclosed. It includes a voltage-controlled oscillator (4,4', 4a, 4b), a switching circuit (28, 28', 28a, 28b) for changing one of two input frequency-modulated signals toward a control input of the voltage-controlled oscillator, and a phase detector (10) for detecting a difference in phase between the frequency-modulated signal reproduced from the recording medium and the output signal of the voltage-controlled oscillator. In a recording operation, an input audio signal is supplied to a control signal input terminal of the voltage-controlled oscillator (VCO) through the switching circuit, and the VCO acts as a modulator for carrying out frequency modulation. In a reproducing operation, the output signal of the phase detector is supplied to the control signal input terminal of the VCO through the switching circuit to form a demodulator having a phase locked loop configuration, and the frequency-modulated signal reproduced from the recording medium is demodulated by the demodulator. A single VCO is used as the VCO for forming the modulator in the recording operation, and is used as the VCO for forming the demodulator having the phase locked loop configuration in the reproducing operation.

公开(公告)号：EP0119635A3

公开(公告)日：1986-03-26

申请号：EP84103175

申请日：1984-03-22

申请人： SONY CORPORATION

发明人： Emori, Takahisa ,  Kikuchi, Masafumi

IPC分类号： H03C03/00

CPC分类号： H03C3/00

摘要： A frequency modulating circuit (10) for modulating a carrier signal by a modulating signal (S,) is disclosed which includes a band-pass filter (10A) of biquad type having a first integrating circuit (12A) and a second integrating circuit (128), an output of the first integrating circuit (12A) being supplied to an input terminal of the second integrating circuit (12B) and an output of the second integrating circuit (12B) being supplied to an input terminal of the first integrating circuit (12A) and the input terminal of the second integrating circuit (12B), and a limiting amplifier circuit (10B) supplied with a part of the output signal of the band-pass filter (10A) and the output thereof being positively fed back to the band-pass filter (10A). In this case, the modulating signal (S l ) is supplied to the first and second integrating circuits (12A, 12B) such that the center frequency of the band-pass filter (10A) is linearly controlled by the modulating signal (S,) whereby a frequency modulated signal (Sm) modulated by the modulating signal (S,) is led out of the output terminal (11) of the second integrating circuit (12B).

公开(公告)号：EP0125811A3

公开(公告)日：1987-06-03

申请号：EP84302664

申请日：1984-04-19

申请人： MARCONI INSTRUMENTS LIMITED

发明人： Owen, David Paul

IPC分类号： H03C03/00

CPC分类号： H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/081 ,  H03L7/1976

摘要： A signal generator is arranged to produce frequency or phase modulation at frequencies which extend from a high value down to zero, i.e. to a d.c. level shift. The output oscillator forms part of a phase locked loop which also includes a variable frequency divider. A modulation signal is applied to the loop, so that high frequency modulation signals directly modify the control signal which determines the frequency of the oscillator, and so that low frequency modulation signals alter the divisor value of the variable frequency divider so as to modify the frequency characteristics of the phase locked loop. Quantisation noise is reduced by applying a masking signal to an analogue-to-digital converter which utilises the low frequency modulation signals to alter the divisor value.

公开(公告)号：EP0068535A3

公开(公告)日：1983-03-09

申请号：EP82200668

申请日：1982-06-02

申请人： Philips Patentverwaltung GmbH ,  N.V. Philips' Gloeilampenfabrieken

发明人： Demmer, Walter ,  Rabeler, Thorwald

IPC分类号： H04L27/12 ,  H03C03/00 ,  H04N05/92 ,  H03K07/06 ,  H03K13/02

CPC分类号： B23K7/00 ,  B23K7/06 ,  B23K7/08 ,  F23D14/56 ,  G11B20/06 ,  H03C3/00 ,  H03C2200/0029 ,  H03K7/06 ,  H04N5/92

摘要： Das modulierende Steuersignal wird in digitaler Form einer Akkumulator aus einem Addierer und einem nachgeschalteten Register zugeführt, so dass eine Folge von Dualzahlen entsprechend einem digitalisierten säge zahnförmigen Signal gebildet wird, bei dem die Modula tionsinformation in der Steigung des Sägezahns liegt. Durch Nachschaltung eines Komplementbildners, der bei jedem zweiten Übertragssignal des Addierers auf Kom plementbildung umgeschaltet wird, wird jede zweite Pe riode des sägezahnförmigen Signals quasi umgeklappt und ein dreieckförmiges Signal mit halber Frequenz gebildet. Durch einen Zuordner mit einem Festwerk speicher kann das digitale dreiecksförmige Signal in ein digitales sinusförmiges Signal umgewandelt werden. Anstart im Komplementbildner kann auch das vom Ak kumulator gelieferte digitale dreiecksförmige Signal di rekt im Zuordner in ein sinusförmiges Signal umgewan delt werden, wobei dann jedoch eine doppelte Speicher kapazität notwendig ist. Ein bevorzugtes Anwendungs gebiet besteht bei Video-Magnetbandgeräten.

摘要翻译： 调制控制信号以数字形式提供给由加法器和寄存器组成的累加器，从而形成对应于数字化锯齿形信号的二进制数序列，其中调制信息位于锯齿形斜率 。 通过随后连接互补形成电路，该补码形成电路被切换成与加法器的每个第二进位信号形成补码，锯齿形信号的每第二周期被折叠，并且具有一半频率的三角形信号 形成。 可以通过包括只读存储器的分配电路将数字三角形信号转换成数字正弦信号。 由积分器提供的数字三角形信号也可以在分配电路中直接转换为正弦信号，而不是在补码形成电路中转换成正弦信号，但在这种情况下，需要两倍的存储容量。 在视频磁带设备的情况下存在优选的应用领域。