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    PROCESSING VECTORIZED GUEST PHYSICAL ADDRESS TRANSLATION INSTRUCTIONS
    3.
    发明公开
    PROCESSING VECTORIZED GUEST PHYSICAL ADDRESS TRANSLATION INSTRUCTIONS 审中-公开

    公开(公告)号：EP3709159A1

    公开(公告)日：2020-09-16

    申请号：EP20154194.3

    申请日：2020-01-28

    申请人： Intel Corporation

    发明人： ZHANG, Fan ,  RICHARDSON, Bruce

    IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/455

    摘要： Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.

    APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE
    5.
    发明公开
    APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE 审中-公开

    公开(公告)号：EP3394733A1

    公开(公告)日：2018-10-31

    申请号：EP16879893.2

    申请日：2016-12-14

    申请人： INTEL Corporation

    发明人： BEN-KIKI, Oren ,  PARDO, Ilan

    IPC分类号： G06F9/34

    CPC分类号： G06F9/30043 ,  G06F9/30065 ,  G06F9/3455

    摘要： An apparatus and method are described for retrieving elements from a linked structure. For example, one embodiment of an apparatus comprises: a decode unit to decode a first instruction, the first instruction to utilize a current address value, an end address value, and an offset; and an execution unit to execute the first instruction to cause the execution unit to compare the current address value with the end address value, the execution unit to perform no additional operation with respect to the first instruction if the current address value is equal to the end address value; and if the current address value is not equal to the end address value, then the execution unit to add the offset value to the current address value to identify a next address pointer within an element structure, the execution unit to further set the current address value equal to the next address pointer.

    A METHOD FOR ENLARGING DATA MEMORY IN AN EXISTING MICROPROCESSOR ARCHITECTURE WITH LIMITED MEMORY ADDRESSING
    6.
    发明公开
    A METHOD FOR ENLARGING DATA MEMORY IN AN EXISTING MICROPROCESSOR ARCHITECTURE WITH LIMITED MEMORY ADDRESSING 审中-公开

    公开(公告)号：EP3323039A1

    公开(公告)日：2018-05-23

    申请号：EP16742534.7

    申请日：2016-07-14

    申请人： Microchip Technology Incorporated

    发明人： KILZER, Kevin ,  JULICHER, Joseph ,  VAN EEDEN, Jacobus Albertus

    IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/35

    摘要： A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

    ADDRESS GENERATION IN A DATA PROCESSING APPARATUS
    9.
    发明公开
    ADDRESS GENERATION IN A DATA PROCESSING APPARATUS 有权
    地址生成的计算设备

    公开(公告)号：EP2652596A1

    公开(公告)日：2013-10-23

    申请号：EP12704438.6

    申请日：2012-01-26

    申请人： ARM Limited

    发明人： STEPHENS, Nigel John ,  SEAL, David James

    IPC分类号： G06F9/34 ,  G06F9/30 ,  G06F9/32 ,  G06F9/355

    CPC分类号： G06F9/3557 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/345 ,  G06F2212/657

    摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.