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公开(公告)号：EP3274817A1
公开(公告)日：2018-01-31
申请号：EP16773692.5
申请日：2016-03-02
申请人： INTEL Corporation
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3004 , G06F9/526
摘要： Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.
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公开(公告)号：EP3394755A1
公开(公告)日：2018-10-31
申请号：EP16879896.5
申请日：2016-12-15
申请人： Intel Corporation
发明人： OREN, Ben-Kiki , PARDO, Ilan
CPC分类号： G06F11/1076 , G06F9/3001 , G06F9/30098 , G06F9/3016 , G06F11/1012
摘要： An apparatus and method are described for enforcement of reserved bits. For example, one embodiment of a processor comprises: a memory management unit to store a set of bits including a set of reserved bits to a system memory; reserved bit enforcement logic to generate a pseudo-random pattern in the reserved bits and an error correction code over the pseudo-random pattern prior to storing the reserved bits; the memory management unit to load the reserved bits including the pseudo-random pattern and the error correction code; the reserved bit enforcement logic to use the error correction code to determine whether the reserved bits have been modified by software; and if the reserved bits have been modified, then the processor to generate an error condition and if not modified, then the processor to continue normal execution.
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公开(公告)号：EP2726959A1
公开(公告)日：2014-05-07
申请号：EP12807775.7
申请日：2012-07-02
申请人： Intel Corporation
发明人： DIEFENBAUGH, Paul S. , GOUGH, Robert E. , BACHRACH, Yuval , HUNSAKER, Mikal C. , BEN-TAL, Rafi , PARDO, Ilan , PRAT, Gideon , HARRIMAN, David J.
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
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公开(公告)号：EP3394733A1
公开(公告)日：2018-10-31
申请号：EP16879893.2
申请日：2016-12-14
申请人： INTEL Corporation
发明人： BEN-KIKI, Oren , PARDO, Ilan
IPC分类号： G06F9/34
CPC分类号： G06F9/30043 , G06F9/30065 , G06F9/3455
摘要： An apparatus and method are described for retrieving elements from a linked structure. For example, one embodiment of an apparatus comprises: a decode unit to decode a first instruction, the first instruction to utilize a current address value, an end address value, and an offset; and an execution unit to execute the first instruction to cause the execution unit to compare the current address value with the end address value, the execution unit to perform no additional operation with respect to the first instruction if the current address value is equal to the end address value; and if the current address value is not equal to the end address value, then the execution unit to add the offset value to the current address value to identify a next address pointer within an element structure, the execution unit to further set the current address value equal to the next address pointer.
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6.发明公开
公开(公告)号：EP3274816A1
公开(公告)日：2018-01-31
申请号：EP16773615.6
申请日：2016-02-05
申请人： Intel Corporation
CPC分类号： G06F9/3822 , G06F9/30087 , G06F9/3009 , G06F9/3806 , G06F9/3851 , G06F9/3877 , G06F9/4843 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/0895 , G06F2212/1016 , G06F2212/283 , G06F2212/452 , G06F2212/6028
摘要： A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.
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