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    FERROELECTRIC MEMORY AND CONTROL APPARATUS THEREFOR, METHOD FOR IMPROVING DURABILITY OF FERROELECTRIC MEMORY, AND DEVICE
    2.
    发明公开
    FERROELECTRIC MEMORY AND CONTROL APPARATUS THEREFOR, METHOD FOR IMPROVING DURABILITY OF FERROELECTRIC MEMORY, AND DEVICE 审中-公开

    公开(公告)号：EP4513493A1

    公开(公告)日：2025-02-26

    申请号：EP23806682.3

    申请日：2023-04-20

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： TAN, Wanliang ,  CAI, Jialin ,  XU, Jeffrey Junhao

    IPC: G11C11/22

    Abstract: Disclosed are a ferroelectric memory, a control apparatus thereof, a method for increasing endurance of the ferroelectric memory, and a device. The control apparatus of the ferroelectric memory includes a signal control unit (90). The signal control unit (90) is coupled to a memory controller (20), an alternating current signal generator (80), and a plate line coupled to a ferroelectric memory cell. The plate line is connected to one end of a ferroelectric capacitor in the ferroelectric memory cell. The signal control unit (90) is configured to switch a signal input to the plate line to a first alternating current signal generated by the alternating current signal generator (80) or a read/write pulse signal output by the memory controller (20), to repair the ferroelectric capacitor via the first alternating current signal when reading/writing is not required. Alternatively, the signal control unit (90) is configured to superimpose a second alternating current signal generated by the alternating current signal generator (80) and the read/write pulse signal, and input a superimposed signal to the plate line, to assist in reading or writing data via the second alternating current signal. This reduces an operating voltage required for ferroelectric switching, reduces damage caused by an electric field to the ferroelectric capacitor, and increases endurance of the device.

    DATA RECEIVING CIRCUIT, DATA RECEIVING SYSTEM, AND STORAGE DEVICE
    3.
    发明公开
    DATA RECEIVING CIRCUIT, DATA RECEIVING SYSTEM, AND STORAGE DEVICE 审中-公开

    公开(公告)号：EP4513490A1

    公开(公告)日：2025-02-26

    申请号：EP22947604.9

    申请日：2022-08-29

    Applicant: Changxin Memory Technologies, Inc.

    Inventor： LIN, Feng

    IPC: G11C7/20 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4072

    Abstract: The present disclosure provides a data receiving circuit, a data receiving system, and a memory device. The data receiving circuit includes: a receiving module, configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module, connected to a feedback node of the receiving module, and configured to perform a decision feedback equalization on the receiving module on the basis of a feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained on the basis of data received previously, and an adjustment capability of the decision feedback equalization module to the first output signal and the second output signal is adjustable.

    MEMORY
    4.
    发明公开
    MEMORY 审中-公开

    公开(公告)号：EP4513489A1

    公开(公告)日：2025-02-26

    申请号：EP23883985.6

    申请日：2023-02-03

    Applicant: CXMT Corporation

    Inventor： LUO, Yifei ,  BA, Hangtian

    IPC: G11C7/12

    Abstract: The present disclosure provides a memory, including: a first-stage amplifier circuit, connected to a bit line and a complementary bit line, and configured to amplify a voltage difference between the bit line and the complementary bit line; a second-stage amplifier circuit, connected to a local data line and a complementary local data line, further connected to a global data line and a complementary global data line, amplifying a voltage difference between the local data line and the complementary local data line after the local data line is connected to the bit line and the complementary local data line is connected to the complementary bit line, and generating a voltage difference between the global data line and the complementary global data line; and a driving circuit, connected to the local data line and the complementary local data line, and amplifying the voltage difference between the local data line and the complementary local data line. Through such a disposition, an impact of coupling capacitors on voltages on local data lines is compensated for, a time for amplifying the voltage difference between the local data line and the complementary local data line can be shortened, and performance of a timing parameter of the memory can be improved.

    DYNAMIC PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS
    5.
    发明公开
    DYNAMIC PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS 审中-公开

    公开(公告)号：EP4513487A2

    公开(公告)日：2025-02-26

    申请号：EP25150447.8

    申请日：2020-11-26

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： GUO, Jason ,  TANG, Qiang

    IPC: G11C5/06

    Abstract: A method of peak power management (PPM) for a memory chip with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the memory chip; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the memory chip is less than a maximum total current allowed for the memory chip.

    NON-VOLATILE MEMORY DEVICE, CORRESPONDING METHOD AND SYSTEM
    6.
    发明公开
    NON-VOLATILE MEMORY DEVICE, CORRESPONDING METHOD AND SYSTEM 审中-公开

    公开(公告)号：EP4513486A1

    公开(公告)日：2025-02-26

    申请号：EP24192638.5

    申请日：2024-08-02

    Applicant: STMicroelectronics International N.V.

    Inventor： PERRONI, Maurizio Francesco ,  DISEGNI, Fabio Enrico Carlo ,  TORTI, Cesare ,  MANFRE', Davide ,  CARUSO, Massimo

    IPC: G11C5/02 ,  G11C7/18 ,  G11C13/00

    Abstract: A device (20), comprising a memory array (28) comprising memory cells arranged in a set of memory portions (280, 282) and addressable via a pair of row and column values, wherein each memory portion in the set of memory portions (280, 282) comprises at least one sector of memory cells (S) arranged in rows and columns. The device (20) comprises: a set of sense amplifier circuits (240) coupled to and interposed adjacent memory portions in the set of memory portions (280, 282) of the memory array (28); a control circuit (CL) configured to provide at least one address signal (AS) indicative of a pair of row and column values to localize at least one addressed memory cell in the memory array (28), the control circuit (CL) being further configured to issue read or write access requests towards the at least one addressed memory cell in the memory array (28); a first set of access devices (YO) configured to be made conductive to couple (LBL) an addressed memory cell in a respective memory portion of the set of memory portions (280, 282) of the memory array (28) to the respective sense amplifier circuit in the set of sense amplifier circuits (240) in response to a read access request issued by the control circuit (CL); a second set of access devices (11) configured to be made conductive to couple an addressed memory cell in a respective memory portion of the set of memory portions (280, 282) of the memory array (28) to the programming bitline (WL) in response to a write access request issued by the control circuit (CL).

    METHOD AND APPARATUS FOR DETERMINING MEMORY FAULT REPAIR MODE, AND STORAGE MEDIUM
    10.
    发明公开
    METHOD AND APPARATUS FOR DETERMINING MEMORY FAULT REPAIR MODE, AND STORAGE MEDIUM 审中-公开

    公开(公告)号：EP4510137A1

    公开(公告)日：2025-02-19

    申请号：EP23841922.0

    申请日：2023-06-01

    Applicant: xFusion Digital Technologies Co., Ltd.

    Inventor： ZHANG, Guangbiao ,  BAO, Quanyang ,  WEI, Weiwei ,  LI, Sheng ,  GAN, Yan ,  CAO, Rui

    IPC: G11C29/44

    Abstract: Embodiments of this application provide a method for determining a memory fault repair manner, an apparatus, and a storage medium, which relate to the field of computer technologies, and can improve memory reliability. The method includes: obtaining information about a plurality of row faults, where information about a row fault includes a ranking of the row fault and a severity of the row fault, an occurrence ranking of the row fault is a quantity of row faults occurring on a memory within a target time period, and the target time period is a time period from a last restart time of a server in which the memory is located to an occurrence time of the row fault; determining a first target row fault from the plurality of row faults based on a severity of each of the plurality of row faults; and determining a repair manner of the first target row fault based on an occurrence ranking of the first target row fault and a severity of the first target row fault.

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