公开(公告)号：EP3460992B1

公开(公告)日：2023-06-28

申请号：EP17192641.3

申请日：2017-09-22

Inventor： Demuth, Thomas ,  Muhamad Ikhwan, Bin Ismail ,  Ebersberger, Sebastian

IPC: H02P25/22 ,  H03D13/00 ,  H02M7/493 ,  H03L7/08 ,  H02M3/158

公开(公告)号：EP4167487A1

公开(公告)日：2023-04-19

申请号：EP22186206.3

申请日：2022-07-21

Applicant: MediaTek Inc.

Inventor： LEE, Fong-Wen ,  WANG, Wen-Chieh ,  LIN, Yu-Hsin

IPC: H03L7/08 ,  H03L7/087 ,  G01R25/00 ,  H03D13/00

Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

公开(公告)号：EP2633620B1

公开(公告)日：2018-02-28

申请号：EP11836846.3

申请日：2011-10-13

Applicant: Marvell World Trade Ltd.

Inventor： WANG, Xiaoyue ,  JAMAL, Shafiq M.

IPC: H03D13/00 ,  H03L7/095 ,  H03L7/199

CPC classification number: H03L7/095 ,  H03L7/199

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

公开(公告)号：EP3244557A1

公开(公告)日：2017-11-15

申请号：EP16305548.6

申请日：2016-05-11

Applicant: ALCATEL LUCENT

Inventor： KOCH, Werner

IPC: H04J3/14 ,  G01R25/00 ,  H04J3/06 ,  H03D13/00

CPC classification number: H04J3/14 ,  G01R25/00 ,  H04J3/0685 ,  H04J3/0697

Abstract: This application relates to a method for supervising a frequency of a main clock signal. The method comprises: measuring a plurality of first frequency values of the main clock signal based on an external time signal, measuring a plurality of second frequency values of the main clock signal based on a local reference signal, comparing the measured plurality of first frequency values of the main clock signal, comparing the measured plurality of second frequency values of the main clock signal, determining a relative long-term frequency change between the main clock signal and the external time signal based on the comparison of the measured plurality of first frequency values of the main clock signal and determining whether a relative frequency change exists between the main clock signal and the local reference signal based on the comparison of the measured plurality of second frequency values of the main clock signal. The application further relates to a frequency supervision apparatus for supervising a frequency of a main clock signal.

Abstract translation: 本申请涉及用于监控主时钟信号的频率的方法。 该方法包括：基于外部时间信号测量主时钟信号的多个第一频率值，基于本地参考信号测量主时钟信号的多个第二频率值，将测量的多个第一频率值 比较主时钟信号的测量的多个第二频率值，基于测量的多个第一频率值的比较来确定主时钟信号与外部时间信号之间的相对长期频率变化 并且基于所测量的主时钟信号的多个第二频率值的比较来确定主时钟信号和本地参考信号之间是否存在相对频率变化。 本申请还涉及一种用于监控主时钟信号的频率的频率监控装置。

公开(公告)号：EP3155719A1

公开(公告)日：2017-04-19

申请号：EP15806097.0

申请日：2015-05-18

Applicant: Catena Holding bv

Inventor： VAN DER CAMMEN, Peter

IPC: H03D7/14 ,  G01R25/00 ,  H03D13/00

CPC classification number: G01R25/00 ,  G01R25/02 ,  G01R25/04 ,  H03D7/14 ,  H03D7/1433 ,  H03D7/1458 ,  H03D13/00 ,  H03K5/26

Abstract: The method determines an input phase differential (Δφ) between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R1) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R2) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R1) and the second impedance (R2) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential (Δφ) is determined when the differential mode output voltage (Vdm) is zero.

Abstract translation: 该方法确定两个输入信号之间的输入相位差（Δφ）。 提供一种相位检测器，其具有成对的晶体管和连接到承载第一信号（Iout_left）的第一分支和连接到承载第二信号（Iout_right）的第二分支的第二阻抗（R2））的第一阻抗（R1）。 第一分支中的第一信号（Iout_left）被设置为共模输出信号（Icm）和差模输出信号（Idm）的第一和。 第二分支中的第二信号（Iout_right）被设置为共模输出信号（Icm）减去差模输出信号（Idm）的第二和。 调整第一阻抗（R1）和第二阻抗（R2）之间的关系，直到相位检测器的差模输出电压（Vdm）为零为止。 当差分模式输出电压（Vdm）为零时，确定输入相位差（Δφ）。

公开(公告)号：EP2983290A1

公开(公告)日：2016-02-10

申请号：EP14290234.5

申请日：2014-08-07

Applicant: NXP B.V.

Inventor： Tourret, Jean-Robert

IPC: H03D13/00 ,  H05B6/68

CPC classification number: H03H17/08 ,  H03D13/00 ,  H05B6/686 ,  H05B6/705 ,  H05B6/72 ,  Y02B40/143 ,  Y02B40/146

Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

Abstract translation: 一种用于检测施加到RF信号的相移量的RF电路和方法。 一种RF加热设备，包括RF电路。 RF电路包括一个移相器，可操作以将相移施加到参考信号以产生相移基准信号。 RF电路还包括相位检测器，其可操作以检测相移RF信号和相移参考信号之间的相位差。 相位检测器在相移RF信号的频率处具有减小的输入范围。 RF电路还包括控制器，其可操作以控制移相器设置相移参考信号的相位，使得相移RF信号和相移参考信号之间的相位差落在相位检测器的减小的输入范围内 。

公开(公告)号：EP2926339A1

公开(公告)日：2015-10-07

申请号：EP12889204.9

申请日：2012-11-27

Applicant: Nokia Technologies OY

Inventor： OJANPERA, Juha Petteri

IPC: G11B27/10 ,  G11B27/022 ,  H03D13/00 ,  H03K5/26 ,  H04J3/00 ,  H04L27/26 ,  H04W56/00

CPC classification number: G11B27/031 ,  G11B27/022 ,  G11B27/10 ,  H04H60/04 ,  H04H60/58

Abstract: An apparatus comprising: an input configured to receive an audio signal; a pairwise selector configured to pairwise select the audio signal and a further audio signal, the further audio signal being a verified audio signal; an offset determiner configured to determine an audio signal time offset between the audio signal and the further audio signal; a similarity predictor configured to generate a similarity index based on the time offset applied to one of the audio signal and the further audio signal when compared against the other of the audio signal and the further audio signal; a verifier configured to verify the audio signal time offset based on the similarity index; and a common time line controller configured to generate a common time line incorporating the audio signal.

公开(公告)号：EP2633620A2

公开(公告)日：2013-09-04

申请号：EP11836846.3

申请日：2011-10-13

Applicant: Marvell World Trade Ltd.

Inventor： WANG, Xiaoyue ,  JAMAL, Shafiq M.

IPC: H03D13/00

CPC classification number: H03L7/095 ,  H03L7/199

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract translation: 指示目标信号与参考信号同相的锁定信号包括在目标信号的上升沿和下降沿检测参考信号。 在参考信号的上升沿和下降沿检测目标信号。 使用目标和参考信号之间的相位不同的状态来将定时装置置于复位状态。 当定时装置被允许超时时，确定信号被指示目标信号被认为被锁定到参考信号。

公开(公告)号：EP2082477A4

公开(公告)日：2013-07-24

申请号：EP07854621

申请日：2007-11-13

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： CRENSHAW DAVID B

IPC: H03D13/00 ,  H02J7/00 ,  H02J9/02

CPC classification number: H02J7/0029 ,  H02J9/02 ,  H02J2007/0037 ,  H02M1/10

公开(公告)号：EP1844542B1

公开(公告)日：2012-04-11

申请号：EP06717679.2

申请日：2006-01-06

Applicant: Skyworks Solutions, Inc.

Inventor： YOUSSOUFIAN, Edward

IPC: H03D13/00 ,  H03L7/085

CPC classification number: H03L7/085 ,  H03D13/003

Abstract: According to one exemplary embodiment, a digital phase detector includes a phase/frequency detector, where the phase/frequency detector is configured to receive a reference signal and a divided oscillator feedback signal and output a first pulse-width modulated signal and a second pulse-width modulated signal. The digital phase detector also includes a first time-to-digital converter, where the first time-to-digital converter is coupled to the phase/frequency detector. The first time-to-digital converter is configured to receive and convert the first pulse-width modulated signal to a first digital number. The digital phase detector further includes a second time-to-digital converter coupled to the phase/frequency detector and configured to receive and convert the second pulse-width modulated signal to a second digital number. The digital phase detector further includes a summation element, where the summation element is configured to subtract the second digital number from the first digital number and output a digital phase error signal.