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    A DETECTOR DEVICE
    1.
    发明公开
    A DETECTOR DEVICE 审中-公开

    公开(公告)号：EP4415268A1

    公开(公告)日：2024-08-14

    申请号：EP23156114.3

    申请日：2023-02-10

    申请人： NXP B.V.

    发明人： Hardeman,, Gijsbert Willem ,  Rutten,, Robert ,  Pol,, Evert-Jan Daniel ,  Liu,, Qilong ,  Bajoria,, Shagun ,  Breems,, Lucien Johannes

    IPC分类号： H03M1/10 ,  H03M1/14 ,  H03M3/00

    CPC分类号： H03M1/1033 ,  H03M1/14 ,  H03M3/414

    摘要： A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.

    CALIBRATION OF DIGITAL-TO-ANALOG CONVERTERS
    9.
    发明公开
    CALIBRATION OF DIGITAL-TO-ANALOG CONVERTERS 审中-公开

    公开(公告)号：EP4258553A1

    公开(公告)日：2023-10-11

    申请号：EP23158077.0

    申请日：2023-02-22

    申请人： Analog Devices, Inc.

    发明人： ENGEL, Gil ,  WILKINS, Paul S.

    IPC分类号： H03M1/10 ,  H03M1/66

    摘要： Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.

    DIFFERENTIAL PHASE ADJUSTMENT OF CLOCK INPUT SIGNALS
    10.
    发明公开
    DIFFERENTIAL PHASE ADJUSTMENT OF CLOCK INPUT SIGNALS 审中-公开

    公开(公告)号：EP4087137A1

    公开(公告)日：2022-11-09

    申请号：EP22174577.1

    申请日：2017-02-07

    申请人： Analog Devices, Inc.

    发明人： CLARA, Martin ,  ENGEL, Gil

    IPC分类号： H03M1/10 ,  H03K5/13 ,  H03M1/12 ,  H03M1/66 ,  H03K5/00

    摘要： Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.