公开(公告)号：JPS62501322A

公开(公告)日：1987-05-21

申请号：JP50509585

申请日：1985-11-06

IPC: H03K3/286 ,  H03K3/2885 ,  H03K23/66

公开(公告)号：JPS6159008B2

公开(公告)日：1986-12-15

申请号：JP1116878

申请日：1978-02-02

Applicant: NIPPON ELECTRIC CO

Inventor： TANAKA HIROSHI

IPC: H03K3/286 ,  H03K3/2885

公开(公告)号：JPS61501350A

公开(公告)日：1986-07-03

申请号：JP50110485

申请日：1985-02-22

IPC: G11C11/34 ,  G05F3/22 ,  G11C7/06 ,  H03F1/30 ,  H03K3/011 ,  H03K3/2885

公开(公告)号：JPS6115422A

公开(公告)日：1986-01-23

申请号：JP13623684

申请日：1984-06-30

Applicant: Sony Corp

Inventor： SHIYOUJI NORIO ,  TAKEDA HITOSHI

IPC: H03K3/286 ,  H03K3/2885 ,  H03K19/086

CPC classification number: H03K3/2885 ,  H03K19/086

Abstract: PURPOSE: To miniaturize the circuit and to reduce power consumption by applying an input level-shifted to a reference voltage side of an ECL logic circuit of differential amplifier constitution to eliminate the need for the reference voltage.
CONSTITUTION: One B
- of logical inputs is fed to a base of a transistor (TR)11 of the reference voltage side of input TRs 1, 11 of differential amplifier constitution in place of a reference voltage, the input B
- is used as an input subject to 1/2 VL level shift in the L and H levels for the amplitude VL to the logical input A fed to the base of the input TR1 and an output is obtained via emitter follower TRs 7, 17. Then no reference voltage is required and number of components such as TRs and resistors is reduced remarkably.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过将输入电平移位到差分放大器结构的ECL逻辑电路的参考电压侧，以消除对参考电压的需要，从而使电路小型化并降低功耗。 构成：一个逻辑输入端被馈送到差分放大器结构的输入TRs1,11的参考电压侧的晶体管（TR）11的基极，代替参考电压，输入B-用作 在输入到输入TR1的基极的逻辑输入端A的振幅VL的L和H电平中输入1/2VL电平移位的输入，并且通过射极跟随器TR7,7获得输出。然后没有参考电压 所需的和诸如TR和电阻器的组件的数量显着降低。

公开(公告)号：JPS6115415A

公开(公告)日：1986-01-23

申请号：JP13623784

申请日：1984-06-30

Applicant: Sony Corp

Inventor： TAKEDA HITOSHI ,  SHIYOUJI NORIO ,  NARISAWA KEIJI

IPC: H03K3/286 ,  H03K3/0233 ,  H03K3/2885

CPC classification number: H03K3/2885

Abstract: PURPOSE:To reduce a delay time by constituting an RSFF of a logical circuit not requiring a reference voltage to decrease the number of components. CONSTITUTION:One logical circuit consists of transistors (TRs) 1, 2, 3, 7, 10, the other logical circuit consists of TRs 21, 22, 23, 27, 30 and each circuit consists of a differential amplifier. Then a set input S and set input control signals A, B are supplied to one NOR gate and a reset input R and reset input control signals C, D are supplied to the other NOR gate. Then terminals A, B, C, D constitute an inhibiting gate ro realize a synchronous type. In this case, the terminals A- D have high/low levels shifted lower to a half of logical amplitude (VL) of the output and have identical VL to each other.

Abstract translation: 目的：通过构成不需要参考电压的逻辑电路的RSFF来减少组件数量来减少延迟时间。 构成：一个逻辑电路由晶体管（TRs）1,2,3,4,10组成，另一个逻辑电路由TR 21,22,23,27,30组成，每个电路由差分放大器组成。 然后将设定输入S和设定输入控制信号A，B提供给一个或非门，复位输入R和复位输入控制信号C，D提供给另一个或非门。 然后端子A，B，C，D构成禁止门，实现同步型。 在这种情况下，终端A-D具有从输出的逻辑振幅（VL）的下半部分移位的高/低电平，并且具有彼此相同的VL。

公开(公告)号：JPS6058554B2

公开(公告)日：1985-12-20

申请号：JP11019378

申请日：1978-09-07

Applicant: SIEMENS AG

Inventor： KURAUSU DERUKAA ,  UIRUHERUMU UIRUHERUMU

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  H03K3/2885

公开(公告)号：JPS6089128A

公开(公告)日：1985-05-20

申请号：JP19677483

申请日：1983-10-20

Applicant: JAPAN RADIO CO LTD

Inventor： ASARI GOROU

IPC: H03K23/00 ,  H03K3/286 ,  H03K3/2885

Abstract: PURPOSE:To reduce number of elements and to expand an output amplitude by constituting a circuit converting a signal into a signal having a half frequency so that its output terminal receives a potential of a collector of a transistor (TR) in a way of an AND gate. CONSTITUTION:A non-inverting output terminal 15 receives a potential of the collector C2 of TRs 35, 36 in a manner of AND gate and an inverting output terminal 16 receives a potential of a collector C3 of TRs 34, 37 in a manner of AND gate. Thus, a clock having a double pulse width and the same 1/2 duty ratio as the clock inputted to a non-inverting input terminal 1 and an inverting input terminal 2, i.e., a clock of a half frequency is outputted to the non-inverting output terminal 15 and the inverting output terminal 16.

公开(公告)号：JPS6072314A

公开(公告)日：1985-04-24

申请号：JP17915183

申请日：1983-09-29

Applicant: TOSHIBA KK

Inventor： TORII KENICHI ,  YOSHIZAWA TOSHIYASU

IPC: H03K3/0233 ,  H03K3/2885

Abstract: PURPOSE:To make high-speed, high-accuracy voltage comparison, by comparing falling characteristics of voltages produced at ends of load resistance with each other and using the characteristics as those, on which tracking is made, even after high-speed sampling is made. CONSTITUTION:When the level of an input voltage at a terminal 1 is slightly lower than that of a reference voltage at another terminal 2, a voltage V2 rapidly falls more than another voltage V1 since more electric current flows to a transistor (TR) TR2. Therefore, emitter follower TRs TR7 and TR8 receive the differential voltage in the next latch mode and latch circuit TRs TR3 and TR4 operate. Moreover, in the latch mode, the voltages V1 and V2 of load resistances tend to rise to a supply voltage VCC while discharging since no electric current flows to TRs TR1 and TR2, but the potential difference is small when the potential difference between the terminals 1 and 2 is small and only this differential voltage and a potential difference which is sufficient to drive the emitter follower of the next stage are produced. Therefore, a differential voltage can be detected accurately even when high-speed sampling is made.

公开(公告)号：JPS59219014A

公开(公告)日：1984-12-10

申请号：JP9357983

申请日：1983-05-27

Applicant: NIPPON ELECTRIC IC MICROCOMPUT

Inventor： TANAKA KAZUTOYO

IPC: H03K3/286 ,  H03K3/2885 ,  H03K19/086 ,  G06F7/00

Abstract: PURPOSE:To obtain a circuit possible for operation immediately after application of power by providing a circuit setting the level of a latch circuit to a desired logical output level without initializing after application of power in the latch circuit of a current switching type logical circuit. CONSTITUTION:A potential at a point X is high just after application of power, a transistor(TR)QX is turned on and a current flows to a resistor R3 independently of the state of a TRQ9. Then a base potential of a TRQ7 rises, the TRQ7 is turned on and a TRQ8 is turned off. That is, a current flows to any of TRQY, Q4 and Q5 in the current switching circuit and the current flows in a path in order of maximum potential, R1, QY, Q7, constant current source and minimum potential. The base potential of the TRQ1 is decreased by the voltage drop of the resistor R1, the TRQ1 is turned off, no current flows to resistors R5, R2, then the base potential of the TRQ2 is high, the TRQ2 is turned on and a current flows to the resistor R4. Thus an output Q goes to a high level and an output Q' goes to a low level.

公开(公告)号：JPS59160320A

公开(公告)日：1984-09-11

申请号：JP3281983

申请日：1983-03-02

Applicant: Hitachi Denshi Ltd ,  Hitachi Ltd

Inventor： HOTSUTA MASAO ,  MAIO KENJI ,  OKIGUCHI KOUTAROU ,  YOKOYAMA TOSHIHIKO

IPC: H03M1/14 ,  H03K3/0233 ,  H03K3/2885

CPC classification number: H03K3/2885

Abstract: PURPOSE:To reduce power consumption and to speed up operation by utilizing the working current of a comparator as an output current and placing no current output part as a trailing stage. CONSTITUTION:Transistors (TR) 101 and 102 are input TRs and connected to input terminals of the comparator. Then, TRs 111 and 112 are TRs for latching and constitute what is called a latching comparator which switches and uses an input amplification part and a latch according to an external clock CLK from switching TRs 131 and 132. Buffer TRs 121 and 122 are provided over this latching comparator to lead the collector current out of the latching comparator.

Abstract translation: 目的：通过利用比较器的工作电流作为输出电流来降低功耗并加快运行，并且不将当前输出部分作为后置级。 构成：晶体管（TR）101和102是输入TR并连接到比较器的输入端。 然后，TR 111和112是用于锁存的TR，并且构成所谓的锁存比较器，其根据来自切换TR 131和132的外部时钟CLK切换和使用输入放大部分和锁存器。缓冲器TR 121和122被提供在 该锁存比较器将集电极电流引出锁存比较器。