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3810 条记录 (耗时 0.042 秒)

    Input circuit
    21.
    发明专利
    Input circuit 有权
    输入电路

    公开(公告)号：JP2013093657A

    公开(公告)日：2013-05-16

    申请号：JP2011232899

    申请日：2011-10-24

    申请人： Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

    发明人： KAMIMARU MASARU

    IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0948

    CPC分类号： H03K5/003 ,  H03K19/00361 ,  H03K19/018521

    摘要： PROBLEM TO BE SOLVED: To provide an input circuit configured to convert a high potential signal to a low potential signal, the input circuit operating at an appropriate target inversion potential.SOLUTION: The input circuit comprises: an inverter; a first path control circuit; and a second path control circuit. An input of the inverter is connected to a first node. A target inversion potential is higher than an inversion potential of the inverter. The first path control circuit electrically disconnects the first node from an input terminal if an input potential is lower than the target inversion potential, and electrically connects the first node to the input terminal if the input potential is higher than the target inversion potential. The second path control circuit electrically connects the first node to a ground terminal if the input potential is lower than a second inversion potential lower than the target inversion potential, and electrically disconnects the first node from the ground terminal if the input potential is higher than the second inversion potential.

    摘要翻译： 要解决的问题：为了提供被配置为将高电位信号转换为低电位信号的输入电路，输入电路以适当的目标反转电位工作。

    解决方案：输入电路包括：逆变器; 第一路径控制电路; 和第二路径控制电路。 逆变器的输入连接到第一节点。 目标反转电位高于逆变器的反转电位。 如果输入电位低于目标反转电位，则第一路径控制电路将第一节点与输入端电气断开，并且如果输入电位高于目标反转电位，则将第一节点与输入端电连接。 如果输入电位低于比目标反转电位低的第二反转电位，则第二路径控制电路将第一节点电连接到接地端子，并且如果输入电位高于目标反转电位，则将第一节点与接地端子电连接 第二反演潜力。 版权所有（C）2013，JPO＆INPIT

    Semiconductor circuit
    22.
    发明专利
    Semiconductor circuit 审中-公开
    半导体电路

    公开(公告)号：JP2013085272A

    公开(公告)日：2013-05-09

    申请号：JP2012269770

    申请日：2012-12-10

    申请人： Mitsubishi Heavy Ind Ltd ,  三菱重工業株式会社

    发明人： ISHII SHIGERU ,  YAMAMOTO KENSUKE ,  TAKAHASHI DAISUKE

    IPC分类号： H03K19/003 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0948

    摘要： PROBLEM TO BE SOLVED: To provide a semiconductor circuit having excellent radiation-resistant characteristics.SOLUTION: A semiconductor circuit includes a first circuit block 1 in which a plurality of pMOS transistors 11 and 12 are connected in series, and a second circuit block 2 in which a plurality of nMOS transistors 21 and 22 are connected in series. A gate of at least one pMOS transistor 12 and/or a gate of at least one nMOS transistor 21 are/is connected to an input terminal Vin, and an on-voltage is applied to a gate of at least one the other pMOS transistor 11 and/or a gate of at least one the other nMOS transistor 22.

    摘要翻译： 要解决的问题：提供具有优异耐辐射特性的半导体电路。 解决方案：半导体电路包括其中多个pMOS晶体管11和12串联连接的第一电路块1和多个nMOS晶体管21和22串联连接的第二电路块2。 至少一个pMOS晶体管12的栅极和/或至少一个nMOS晶体管21的栅极被连接到输入端Vin，并且将导通电压施加到至少一个其它pMOS晶体管11的栅极 和/或至少另一个nMOS晶体管22的栅极。（C）2013，JPO和INPIT

    Slew rate control device and slew rate control method
    23.
    发明专利
    Slew rate control device and slew rate control method 有权
    SLEW RATE CONTROL DEVICE AND SLEW RATE CONTROL METHOD

    公开(公告)号：JP2013017086A

    公开(公告)日：2013-01-24

    申请号：JP2011149201

    申请日：2011-07-05

    申请人： Fujitsu Semiconductor Ltd ,  富士通セミコンダクター株式会社

    发明人： MIYATA SHINJI

    IPC分类号： H03K19/0175 ,  H03K19/0948

    摘要： PROBLEM TO BE SOLVED: To provide a slew rate control device and a slew rate control method that suppress EMI noise by performing a slew rate adjustment depending on the frequency of a clock signal in an output buffer of the clock signal.SOLUTION: The slew rate control device includes: a PLL circuit 24a having a voltage-controlled oscillator 15a for converting an input VCO input voltage Vi to a clock signal CK according to a conversion gain Gi; a voltage/current converter 19a for outputting a control current Ib having a positive correlation with each of the VCO input voltage Vi and the conversion gain Gi; a buffer control circuit 21a for setting a driving current according to the control current Ib; and an output circuit 22a for outputting a clock signal CKo in response to the driving current. A relationship can thus be established in which the drivability of the output circuit 22a increases in proportion to a frequency f of the clock signal CKo to determine an appropriate slew rate in accordance with the frequency f.

    摘要翻译： 要解决的问题：提供一种通过根据时钟信号的输出缓冲器中的时钟信号的频率进行压摆率调整来抑制EMI噪声的转换速率控制装置和压摆率控制方法。 解决方案：转换速率控制装置包括：PLL电路24a，具有压控振荡器15a，用于根据转换增益Gi将输入的VCO输入电压Vi转换为时钟信号CK; 电压/电流转换器19a，用于输出与VCO输入电压Vi和转换增益Gi中的每一个具有正相关的控制电流Ib; 用于根据控制电流Ib设定驱动电流的缓冲器控制电路21a; 以及输出电路22a，用于响应于驱动电流输出时钟信号CKo。 因此可以建立输出电路22a的驱动能力与时钟信号CKo的频率f成比例地增加的关系，以根据频率f确定适当的转换速率。 版权所有（C）2013，JPO＆INPIT

    Control signal generating circuit and semiconductor device using the same
    24.
    发明专利
    Control signal generating circuit and semiconductor device using the same 有权
    使用该控制信号生成电路和半导体器件

    公开(公告)号：JP2013009428A

    公开(公告)日：2013-01-10

    申请号：JP2012210743

    申请日：2012-09-25

    申请人： Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

    发明人： MITANI HIDENORI ,  ITO TAKASHI

    IPC分类号： H03K17/22 ,  G11C16/06 ,  H03K19/00 ,  H03K19/0948 ,  H03K23/54

    摘要： PROBLEM TO BE SOLVED: To provide a control signal generating circuit suitable for controlling a semiconductor device.SOLUTION: A Johnson counter 31 includes flip-flops FF1-FF4 and gate circuits 41-44. It changes control signals C1-C4 to an "H" level in response to start signals ST1-ST4 that are sequentially inputted, and then, the control signals C1-C4 are changed to an "L" level in response to stop signals SP1-SP4 that are sequentially inputted. Thus, without using many flip-flops, the control signals C1-C4 are sequentially changed to the "H" level and the "L" level with a desired time interval.

    摘要翻译： 解决的问题：提供适合于控制半导体器件的控制信号发生电路。 解决方案：约翰逊计数器31包括触发器FF1-FF4和门电路41-44。 它响应于顺序输入的开始信号ST1-ST4将控制信号C1-C4改变到“H”电平，然后控制信号C1-C4响应于停止信号SP1- SP4顺序输入。 因此，在不使用多个触发器的情况下，控制信号C1-C4以期望的时间间隔顺序地变更为“H”电平和“L”电平。 版权所有（C）2013，JPO＆INPIT

    Semiconductor device
    25.
    发明专利
    Semiconductor device 有权
    半导体器件

    公开(公告)号：JP2013009313A

    公开(公告)日：2013-01-10

    申请号：JP2012107722

    申请日：2012-05-09

    申请人： Semiconductor Energy Lab Co Ltd ,  株式会社半導体エネルギー研究所

    发明人： KATO KIYOSHI

    IPC分类号： H03K19/0944 ,  H03K17/06 ,  H03K19/0948

    CPC分类号： H03K19/0013 ,  H01L27/12 ,  H01L27/1225 ,  H03K19/0944

    摘要： PROBLEM TO BE SOLVED: To solve the problem with a dynamic logic circuit, one of logic circuits including the dynamic logic circuit and a static logic circuit as semiconductor devices including semiconductor formed using a transistor and the like, in which: the dynamic logic circuit can hold data for a certain period, so that leakage current from the transistor becomes a problem in the dynamic logic circuit as compared with the static logic circuit.SOLUTION: A logic circuit includes a first transistor with small off current and a second transistor whose gate is electrically connected. A charge is supplied to a node of the gate of the second transistor via the first transistor. To the node, the charge is supplied via first and second capacitors. The second transistor is turned on or off depending on the state of the charge. The first transistor has an oxide semiconductor in a channel formation region.

    摘要翻译： 解决的问题为了解决动态逻辑电路的问题，包括动态逻辑电路和静态逻辑电路的逻辑电路之一，包括使用晶体管等形成的半导体器件的半导体器件，其中：动态 逻辑电路可以保持一定时间的数据，使得与静态逻辑电路相比，来自晶体管的漏电流成为动态逻辑电路中的问题。 解决方案：逻辑电路包括具有小截止电流的第一晶体管和栅极电连接的第二晶体管。 经由第一晶体管将电荷提供给第二晶体管的栅极的节点。 通过第一和第二电容器向节点提供电荷。 根据电荷的状态，第二晶体管导通或截止。 第一晶体管在沟道形成区域中具有氧化物半导体。 版权所有（C）2013，JPO＆INPIT

    Semiconductor device
    26.
    发明专利
    Semiconductor device 有权
    半导体器件

    公开(公告)号：JP2013009309A

    公开(公告)日：2013-01-10

    申请号：JP2012105174

    申请日：2012-05-02

    申请人： Semiconductor Energy Lab Co Ltd ,  株式会社半導体エネルギー研究所

    发明人： OSHIMA KAZUAKI

    IPC分类号： H03K19/0175 ,  H03K19/0948

    CPC分类号： H01L27/105 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/108 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/1776 ,  H03K19/17772

    摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes a first transistor with p-type conductivity, a second transistor with n-type conductivity, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wire having a function of supplying a first potential, and the other thereof is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other one of the source and the drain of the first transistor, and the other one of the source and the drain of the second transistor is connected to one of a source and a drain of the fourth transistor. The other one of the source and the drain of the fourth transistor is connected to a wire having a function of supplying a second potential, which is lower than the first potential. For a channel formation region of each of the third transistor and the fourth transistor, an oxide semiconductor material is used.

    摘要翻译： 要解决的问题：提供具有新颖结构的半导体器件。 解决方案：半导体器件包括具有p型导电性的第一晶体管，具有n型导电性的第二晶体管，第三晶体管和第四晶体管。 第三晶体管的源极和漏极之一连接到具有提供第一电位的功能的导线，另一个连接到第一晶体管的源极和漏极之一。 第二晶体管的源极和漏极之一连接到第一晶体管的源极和漏极中的另一个，而第二晶体管的源极和漏极中的另一个连接到源极和源极之一， 第四晶体管的漏极。 第四晶体管的源极和漏极中的另一个连接到具有提供比第一电位低的第二电位的功能的导线。 对于第三晶体管和第四晶体管的沟道形成区域，使用氧化物半导体材料。 版权所有（C）2013，JPO＆INPIT