公开(公告)号：JPS5979615A

公开(公告)日：1984-05-08

申请号：JP18911182

申请日：1982-10-29

Applicant: Hitachi Ltd ,  Hitachi Micro Comput Eng Ltd

Inventor： IRIKURA SHIYOUGO ,  KACHI TADAO

IPC: H03F3/45

Abstract: PURPOSE: To reduce the dispersion of production processes and the difference of temperature distribution between plural constant current circuits by constituting a constant current circuit by plural contact current transistors (TRs) in a differential amplifier circuit and arranging said constant current circuit close to other constant current circuit parts.
CONSTITUTION: A constant current circuit part in each differential amplifier circuit out of plural ones consists of plural constant current TRs, which are arranged close to each other. Thus, the dispersion of production processes, the piezo effect and the difference of bias current due to the temperature difference in a chip can be reduced, improving the matching of amplification factors between plural amplifier circuits.
COPYRIGHT: (C)1984,JPO&Japio

Abstract translation: 目的：通过在差分放大电路中构成多个接触电流晶体管（TRs）的恒流电路，减少生产工艺的分散和多个恒流电路之间的温度分布差异，并将所述恒流电路布置成接近其他恒定电流 电路部分。 构成：多个恒定电流电路中的多个恒定电流部件由多个恒定电流TR组成，它们彼此靠近配置。 因此，可以降低生产过程的分散性，压电效应和由于芯片中的温度差引起的偏置电流的差异，从而改善了多个放大器电路之间的放大系数的匹配。

公开(公告)号：JPS59191911A

公开(公告)日：1984-10-31

申请号：JP6533883

申请日：1983-04-15

Applicant: Hitachi Ltd ,  Hitachi Micro Comput Eng Ltd

Inventor： HIKASA KAZUHIKO ,  KACHI TADAO ,  SEKINE YASUSHI ,  OURA TAKAYUKI

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/0023

Abstract: PURPOSE:To control simply the amplification factor of a differential amplifying circuit with no trimming of a resistance which requires a complicated and exclusive device, by attaining the variable setting of constant current value for a constant current source which limits a working current flowing in common to a pair of active elements. CONSTITUTION:A differential amplifying circuit consists of a pair of transistors TRQ1 and Q2 connected with a load resistance RC respectively and a constant current source 10 which controls a working current flowing in common to the TRQ1 and Q2. Plural constant current circuits consisting of TRQ3, Q4... and resistances R3, R4... connected in series to the emitters of said transistors are connected in series to each other to constitute the source 10. Then an optional constant current circuit selected by operation signals e1, e2... sent from outside and supplied to the bases of the TRQ3, Q4... is actuated. Thus the constant current value is set variably. Thus the amplification factor is controlled variably for the differential amplifying circuit.

Abstract translation: 目的：为了简单地控制差分放大电路的放大系数，不需要修复需要复杂和排他的器件的电阻，通过实现恒定电流源的恒定电流值的可变设置，这限制了共同流动的工作电流 一对活跃元素。 构成：差分放大电路由一对分别与负载电阻RC连接的晶体管TRQ1和Q2组成，恒流源10控制工作电流共同流向TRQ1和Q2。 由串联连接到所述晶体管的发射极的TRQ3，Q4 ...和电阻R3，R4 ...组成的多个恒流电路彼此串联连接以构成源极10.然后，选择一个可选的恒流电路 从外部发送并提供给TRQ3，Q4 ...的基座的操作信号e1，e2 ...被致动。 因此恒定电流值是可变的。 因此，对差分放大电路可变地控制放大系数。

公开(公告)号：JPH05210811A

公开(公告)日：1993-08-20

申请号：JP4013192

申请日：1992-01-30

Applicant: HITACHI LTD

Inventor： YOSHINAGA MAKI ,  HATANAKA NORIAKI ,  HIRAI TOMOAKI ,  NAGAYA YUJI ,  HIROSE TAKESHI ,  KACHI TADAO

IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B5/035 ,  G11B5/40 ,  G11B5/455 ,  G11B19/04

Abstract: PURPOSE:To enable high speed write by imparting a write current dependency to a clamp voltage for suppressing a flyback voltage generated in a magnetic head at the time of a changeover in a current direction. CONSTITUTION:An operating current of differential transistors Q6 and Q7 has a dependency upon a write current IW as IA+IW'. Then, since a collector potential of the transistor Q6 is determined by the operating current (IA+IW ')XRI, the write current dependency can be imparted to the clamp voltage of a write driver. That is, as a result of changing a signal amplitude to be increased in accordance with an increase of the write current IW under the transient state of the write driver, when DELTAi is increased, the clamp voltage V is increased accordingly so as to act to make DELTAt constant.

公开(公告)号：JPS61100705A

公开(公告)日：1986-05-19

申请号：JP22215384

申请日：1984-10-24

Applicant: Hitachi Ltd

Inventor： SHIRAI MASAYUKI ,  OKUYA KEN ,  KACHI TADAO

IPC: G02B6/42

Abstract: PURPOSE: To connect quickly and exactly a light emitting element or photodetector and optical fiber by providing a guide in the prescribed position of the light emitting element, etc.
CONSTITUTION: The guide having the shape suitable for the purpose of matching the center of the light emitting pat 5a of the element 5 and the center of the optical fiber 3 consisting of a core part 3a and a clad part 3b and fixing the fiber in the proximate state as far as possible is provided in the prescribed position of the element 5 so that said purpose is achieved simply by matching the top end of the fiber 3 to the guide. The guide is formed of a lead 6 which is used for electrical connection of the element 5 and the electrode on the top surface of a substrate 2. The lead 6 is the so-called finger lead by tape carrier bonding and is formed by laminating a polyimid resin 6b having a prescribed shape on copper foil 6a and coating further rubber 6c as a cushion material onto the top end surface thereof. The lead 6 is electrically connected to the element by a bump electrode 8 formed to the copper foil 6a part.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过在发光元件等的规定位置提供引导件，快速准确地连接发光元件或光电检测器和光纤。构成：具有适合于匹配光的中心的形状的引导件 在元件5的规定位置设置元件5的发光元件5a和由芯部3a和包层部3b构成的光纤3的中心并将光纤尽可能靠近的状态，使得 所述目的简单地通过将光纤3的顶端与引导件相匹配来实现。 引导件由引线6形成，引线6用于元件5和基板2的顶表面上的电极的电连接。引线6是通过带状载体接合的所谓的指状引线，并且通过层压 在铜箔6a上具有规定形状的聚酰亚胺树脂6b，并将另外的橡胶6c作为缓冲材料涂覆到其顶端表面上。 引线6通过形成在铜箔6a部分上的突起电极8与元件电连接。

公开(公告)号：JPS60171747A

公开(公告)日：1985-09-05

申请号：JP2709884

申请日：1984-02-17

Applicant: HITACHI MICROCUMPUTER ENG ,  HITACHI LTD

Inventor： YUURAKU TAKAYUKI ,  KACHI TADAO ,  OKINAGA TAKAYUKI ,  SHIRAI MASAYUKI

IPC: H05K1/18 ,  H01L23/04 ,  H01L23/12 ,  H01L23/498 ,  H05K3/34

Abstract: PURPOSE:To avoid the titled device to be subjected to the effect of the migration of a current, and to enhance reliability of said device by a method wherein the corner parts of the package of the semiconductor device are beveled, and wirings are formed on the outside surface of a substrate. CONSTITUTION:The corner parts of the ceramic substrate 4 of a package are chipped off (beveled) aslant, and thick film wirings 7 are formed on the substrate thereof. The wirings 7 consist of the parts 7A formed on the surface of the ceramic substrate 4 and bonded with connector wires, the part 7B extended to the parts thereof and formed on the sides of the substrate, and the parts 7C formed on the back of the substrate, for example. The back wirings 7C are constructed as solderable electrodes, and the chip carrier type ceramic package 3 is connected to the conductor pattern 2 surface of a printed substrate 1 by soldering the electrodes. Beveling is performed by forming curves of fixed curvature to the corner parts of the ceramic substrate 4, the wirings 7 are formed on the substrate 4, and film thickness t3 of the thick film wirings at the corner parts may be made to the same or more of film thickness t2 of the other parts.

公开(公告)号：JPS5712564A

公开(公告)日：1982-01-22

申请号：JP8661280

申请日：1980-06-27

Applicant: HITACHI LTD

Inventor： KACHI TADAO

IPC: H01L29/47 ,  H01L29/872

Abstract: PURPOSE:To reduce unevenness of positive directional characteristic of a semiconductor device by a method wherein an n type buried layer is provided adjoining to an n type buried layer, and is made to face with a metal on the surface forming a Schottky barrier interposing an epitaxial layer between them. CONSTITUTION:As ions ar driven in a p type Si substrate 1 to form the n type layer 2, P ions are driven in partially to form the n type layer 11, and when the n type epitaxial layer 3 is accumulated thereon, the buried layer 11 diffuses greatly in the epitaxial layer. The n type layer 3 is isolated 13 with the p type layer, p type base region 4 is provided and an n type base region 5, an n type collector lead out layer 6 are formed in succession. An opening is formed in an SiO2 film 12 on the surface facing with the buried layer 11 to evaporated Al, and sintering is performed to form a Schottky barrier 8. Then an ohmic wiring 7 is provided, and the base layer 4 and the Schottky barrier are connected. By this constitution, because the buried layer 11 is extended toward the Schottky barrier, the value of series resistance to be generated by unevenness of specific resistance is reduced even when epitaxial layer 3 is thick, positive directional characteristic of the Schottky diode is equalized and yield is enhanced.

公开(公告)号：JPS5571326A

公开(公告)日：1980-05-29

申请号：JP14421078

申请日：1978-11-24

Applicant: HITACHI LTD

Inventor： KACHI TADAO

IPC: H03K19/086

Abstract: PURPOSE:To realize a low current consumption and a high-speed operation by connecting the collector of an emitter follower circuit, which takes out the output, to a load resistance in the current switching logical operation circuit. CONSTITUTION:Reference voltage VBB is given to transistor Q5, and input transistors Q1 and Q2 are provided correspondingly to the number of input terminals. Transistors Q1 and Q2 are an emitter follower circuit, and NOR and OR outputs are taken out from output terminals O1 and O2. Transistors Q1 and Q2 are the emitter follower circuit which have collectors connected to load resistance R4, and NOR and OR are outputted by transistors Q3-Q5. The value of resistance R4 is determined by currents I1-I3. Then, R4=V1/I1+I2+I3 is true, and R4 can be smaller than the resistance value of the conventional circuit, so that the switching time can be enhanced.

公开(公告)号：JPS5529122A

公开(公告)日：1980-03-01

申请号：JP10179978

申请日：1978-08-23

Applicant: HITACHI LTD

Inventor： KACHI TADAO

IPC: H01L29/80 ,  H01L21/331 ,  H01L29/06 ,  H01L29/73

Abstract: PURPOSE:To shorten distance of an air-lacking layer, to enable low voltage operation to be achieved and to shorten area of an element by providing a part of surrounding of a p gate layer and an n source layer with an insulation film and a p layer. CONSTITUTION:An insulation layer 10 and a p layer 9 are formed to surround an n layer provided with a p gate layer 5 and an n source layer 6. In this structure, distance of an air-lacking layer required for pinch-off is determined by distance x4 between the layers 5 and 9. Further, an element's size x can be approximately 15 mum since it is not necessary to surround an n layer 6 with a p layer. For this reason, it is possible to reduce power consumption by lowering operating voltage and also to reduce the element's size.

公开(公告)号：JPS54100269A

公开(公告)日：1979-08-07

申请号：JP621878

申请日：1978-01-25

Applicant: HITACHI LTD

Inventor： KACHI TADAO

IPC: H01L29/80 ,  H01L21/331 ,  H01L29/06 ,  H01L29/73

Abstract: PURPOSE:To reduce the distance of the effective depletion layer and to lower the active voltage of the electrostatic conduction transistor by deciding the distance of the depletion layer necessary for the pinch-off state with the depth of the diffusion. CONSTITUTION:N -layer 8 to be the drain region later is formed through diffusion on P-type Si substrate 20, and then P -layer 7 is epitaxial-grown on the entire surface to coat Si3N4 film 12 selectively. Then N-type impurity is diffused at the exposed area of layer 7 to form ring-shaped N-type region 13, and SiO2 film 10 reaching layer 8 from the surface is formed through the heat treatment in the oxidizing atmosphere. At the same time, region 13 is diffused to cause N -type chaneel region 9' within layer 7. After this, film 12 is removed, and P gate region 5 and N source region 6 whose one end is adjacent to film 10 and the other end is distant from each other are formed within layer 7 surrounded by film 10 through the selective diffusion with the SiO2 film used as the mask. Then the electrode is attached to region 5 and 6 as well as to layer 8.

公开(公告)号：JPS5443683A

公开(公告)日：1979-04-06

申请号：JP10988177

申请日：1977-09-14

Applicant: HITACHI LTD

Inventor： ANZAI AKIO ,  KACHI TADAO

IPC: H01L29/73 ,  H01L21/31 ,  H01L21/331 ,  H01L29/72

Abstract: PURPOSE:To self-align the emitter and base areas to improve production yield and reduce the base extending resistance to improve high frequency characteristic by forming simultaneously the impurity leading open hole for emitter formation and the impurity leading open hold for base formation. CONSTITUTION:N type buried area 16 is provided on P type Si substrate 12, and N type layer 14 is grown epitaxially throughout the surface, and layer 14 is covered with SiO2 film 18 and Si3N4 film 20. Next, open hole 20a is provided in film 20 on a prescribed area and is subjected to selective oxidation to form SiO2 isolated area 22 which reaches substrate 12, and N type insular area 14A is generated on area 16. After that, P type impurity ions are implanted to form P type active base area 26 on the surface of area 14A, and Si3N4 film 28 is caused to adhere onto film 18. Then, open holes 30 and 34 for base and open hole 32 for emitter are simultaneously formed by etching. Next, P type base areas 40 and 42 are formed in area 14A by diffusion by using open holes 30 and 34, and N type emitter area 50 is formed in area 26 surrounded by them by diffusion by using open hole 32.