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1.
公开(公告)号:KR100451011B1
公开(公告)日:2004-10-02
申请号:KR1020000043629
申请日:2000-07-28
申请人: 샤프 가부시키가이샤
IPC分类号: H01L27/105
CPC分类号: H01L28/55 , C23C16/409 , H01L21/31604 , H01L21/31691
摘要: A ferroelectric device is provided with a single phase, high quality, ferroelectric film orientationally grown on a Pt electrode. The Pt electrode is orientationally grown on a material that has the lattice structure desired in the ferroelectric film. The Pt electrode adopts the lattice structure of the underlying layer, so that lattice mismatch between the Pt and the ferroelectric film is minimized. This adjustment in the Pt lattice structure permits the formation of single phase perovskite ferroelectric films, on Pt electrodes, at low deposition temperatures. As a result, ferroelectric devices with low leakage current, and completely saturated, square, symmetrical hysteresis loops are formed. A method of forming the ferroelectric film, of the above-mentioned ferroelectric device, is also provided.
摘要翻译: 铁电器件具有在Pt电极上取向生长的单相高质量铁电薄膜。 Pt电极取向生长在具有铁电膜所需的晶格结构的材料上。 Pt电极采用下层的晶格结构,使得Pt与铁电薄膜之间的晶格失配最小化。 铂点阵结构中的这种调整允许在低电极温度下在铂电极上形成单相钙钛矿铁电薄膜。 结果,形成了具有低漏电流的铁电器件和完全饱和的方形对称磁滞回线。 还提供了一种形成上述强电介质器件的强电介质膜的方法。 <图像>
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公开(公告)号:KR100437071B1
公开(公告)日:2004-06-23
申请号:KR1020010071075
申请日:2001-11-15
申请人: 샤프 가부시키가이샤
IPC分类号: H01L21/283
CPC分类号: H01L21/28088 , H01L21/28176 , H01L21/28291 , H01L27/10873 , H01L29/4966
摘要: A semiconductor structure includes a substrate taken from the group of substrates consisting of silicon, polysilicon, silicon dioxide and silicon germanium; and an electrode, located above the substrate, which includes a layer of composition Ir-M-O, wherein M is take from the group of metals consisting of Ta, Ti, Nb, Al, Hf, Zr and V; wherein the semiconductor structure is constructed and arranged to withstand annealing at a temperature greater than or equal to 600 DEG C without losing conductivity and integrity. A method of forming a semiconductor structure includes preparing a substrate taken from the group of substrates consisting of silicon, polysilicon, silicon dioxide and silicon germanium; depositing successive layers of materials including depositing an electrode layer of composition Ir-M-O, wherein M is taken from the group of metals consisting of Ta, Ti, Nb, Hf, Zr and V; and annealing the semiconductor structure at a temperature greater than or equal to 600 DEG C.
摘要翻译: 一种半导体结构包括从由硅,多晶硅,二氧化硅和硅锗组成的衬底组中获得的衬底; 以及位于衬底上方的电极,其包括组成为Ir-M-O的层,其中M取自Ta,Ti,Nb,Al,Hf,Zr和V的金属组; 其中所述半导体结构被构造和布置成能够耐受大于或等于600℃的温度下的退火,而不丧失导电性和完整性。 一种形成半导体结构的方法包括:制备从由硅,多晶硅,二氧化硅和硅锗组成的衬底组中得到的衬底; 沉积连续的材料层,包括沉积组成为Ir-M-O的电极层,其中M取自由Ta,Ti,Nb,Hf,Zr和V组成的金属组; 以及在大于或等于600℃的温度下退火该半导体结构。
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公开(公告)号:KR100386539B1
公开(公告)日:2003-06-02
申请号:KR1020000027254
申请日:2000-05-20
申请人: 샤프 가부시키가이샤
IPC分类号: H01L27/105
CPC分类号: H01L21/28291 , H01L21/28568 , H01L28/75 , H01L29/513 , H01L29/516 , H01L29/78391
摘要: An Ir-M-O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir-M-O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays and piezoelectric transducers. A method for forming an Ir-M-O composite film barrier layer with an oxidized refractory metal barrier layer is also provided.
摘要翻译: 已经提供了用于形成铁电电容器的电极的Ir-M-O复合膜,其中M包括各种难熔金属。 Ir组合膜有效地防止了氧扩散,并且耐氧环境中的高温退火。 当与氧化相同种类的M过渡金属制成的底层阻挡层一起使用时,所得到的导电阻挡层也抑制Ir扩散到任何底层Si衬底中。 结果,不会形成Ir硅化物产品,这会降低电极界面特性。 在高温退火过程中,即使在氧气中,Ir组合膜仍保持导电性,不剥落或形成小丘。 Ir-M-O导电电极/阻挡层结构适用于非易失性MFMIS(金属/铁电/金属/绝缘体/硅)存储器件,DRAM,电容器,热释电红外传感器,光学显示器和压电传感器。 还提供了一种用氧化难熔金属阻挡层形成Ir-M-O复合膜阻挡层的方法。 <图像>
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公开(公告)号:KR1020030036055A
公开(公告)日:2003-05-09
申请号:KR1020020066580
申请日:2002-10-30
申请人: 샤프 가부시키가이샤
IPC分类号: H01L29/78
CPC分类号: H01L21/28185 , C23C16/0272 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/3144 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/56 , H01L29/40 , H01L29/513 , H01L29/516 , H01L29/517
摘要: PURPOSE: A method for fabricating a memory device is provided to obtain a metal-ferroelectric-oxide-semiconductor(MFOS) memory device having a high-k insulation layer and a buffering layer between a substrate and a ferroelectric. CONSTITUTION: A silicon substrate is prepared. A layer of high-k insulator is deposited on the silicon substrate. A buffering layer is deposited on the high-k insulation layer. A layer of ferroelectric material is deposited on the buffering layer by metal organic chemical vapor deposition(CVD). A top electrode is formed on the layer of ferroelectric material. A completing process is performed on a device obtained by the abovementioned processes.
摘要翻译: 目的:提供一种用于制造存储器件的方法,以获得具有高k绝缘层和衬底和铁电体之间的缓冲层的金属 - 铁电氧化物半导体(MFOS)存储器件。 构成:制备硅衬底。 在硅衬底上沉积一层高k绝缘体。 缓冲层沉积在高k绝缘层上。 通过金属有机化学气相沉积(CVD)将一层铁电材料沉积在缓冲层上。 顶层电极形成在铁电材料层上。 对通过上述处理获得的装置进行完成处理。
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公开(公告)号:KR100373080B1
公开(公告)日:2003-02-25
申请号:KR1020000022378
申请日:2000-04-27
申请人: 샤프 가부시키가이샤
IPC分类号: H01L27/105
CPC分类号: H01L21/31691 , C23C16/40 , H01L21/31604 , Y10S438/933 , Y10T428/12674 , Y10T428/12701 , Y10T428/12875
摘要: A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650 DEG C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1 x 10 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6 x10 A/cm at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.
摘要翻译: 铁电Pb5Ge3O11(PGO)薄膜具有金属有机气相沉积(MOCVD)工艺和RTP(快速热工艺)退火技术。 PGO薄膜在450-650℃的温度下基本上以c轴取向进行结晶.PGO薄膜具有约0.5微米的平均晶粒尺寸,晶粒尺寸均匀性的偏差小于10%。 具有Ir电极的150nm厚的膜获得良好的铁电性能。 这些薄膜也显示出无疲劳的特征:至多1×10 8没有观察到疲劳。 开关周期。 漏电流随着施加电压的增加而增加,并且大约为3.6×10 -7 阿/厘米2 - ; 在100kV / cm。 介电常数表现出与大多数铁电材料类似的行为,最大介电常数约为45.由于PGO薄膜晶粒尺寸的均匀性,这些高质量MOCVD Pb5Ge3O11薄膜可用于高密度单晶体管铁电存储器应用。 <图像>
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公开(公告)号:KR1020030003025A
公开(公告)日:2003-01-09
申请号:KR1020020035877
申请日:2002-06-26
申请人: 샤프 가부시키가이샤
IPC分类号: H01L27/115 , H01L27/10 , H01L27/105 , G11C11/00
CPC分类号: H01L27/24 , G11C11/15 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77
摘要: PURPOSE: A low cross-talk electrically programmable resistance cross point memory is provided to aid in the programming and readout of a bit region by including a bit made of a perovskite material interposed at a cross point of an upper electrode and a lower electrode. CONSTITUTION: A substrate is prepared. A plurality of lower electrodes are placed on the substrate. A plurality of upper electrodes cross the lower electrodes to form a cross point at each cross position, placed on the lower electrodes. An active layer is made of a perovskite material, interposed between the plurality of upper electrodes and the plurality of lower electrodes at each cross point.
摘要翻译: 目的:提供低串扰电可编程电阻交叉点存储器,以通过包括插入在上电极和下电极的交叉点处的钙钛矿材料制成的位来帮助编程和读出位区域。 构成:制备底物。 多个下电极放置在基板上。 多个上电极与下电极交叉,在各交叉位置形成交叉点,放置在下电极上。 有源层由钙钛矿材料制成,插入在每个交叉点处的多个上电极和多个下电极之间。
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公开(公告)号:KR100365038B1
公开(公告)日:2002-12-16
申请号:KR1020000022984
申请日:2000-04-28
申请人: 샤프 가부시키가이샤
IPC分类号: H01L21/205
摘要: MOCVD 퇴적 공정은 향상된 PGO 강유전성 막의 퇴적을 위해 제공되었다. 제 1 상 Pb
5 Ge
3 O
11 과 함께 제 2 상 Pb
3 GeO
5 를 포함시키면 향상된 강유전 특성에 직접 상응하는 약간의 강유전 특성을 막에 제공한다. 제 2 상을 포함시키면 제 1 상 결정 입자 크기를 조절하고 입자의 바람직한 c-축 배향을 증진시킨다. 제 2 상 Pb
3 GeO
5 의 정도는 전구체 내에 납의 양을 조절함으로써 조절되고, 납-게르마늄 막을 산화하는데 사용된 산소와 함께 반응기에 납을 추가로 첨가한다. 본 명세서에서는 PGO 막의 강유전 특성을 최적화하는데 중요한 후-퇴적 어닐링 공정을 기재한다. 본 발명의 다상 PGO막을 포함하는 다상 PGO 막과 커패시터 구조를 제공한다.-
公开(公告)号:KR1020020077132A
公开(公告)日:2002-10-11
申请号:KR1020020016678
申请日:2002-03-27
申请人: 샤프 가부시키가이샤
IPC分类号: H01L21/31
CPC分类号: H01L28/65 , C23C16/40 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75 , Y10T428/24917 , Y10T428/2495
摘要: PURPOSE: A single c-axis lead germanium oxide(PGO) thin film electrode having good surface smoothness and uniformity is provided to improve surface roughness of the PGO thin film by forming a uniform, single-phase, c-axis PGO thin film on a metal electrode. CONSTITUTION: A substrate is prepared. An electrode is deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir-Ta-O, Ir-Ti-O, Ir-Nb-O, Ir-Al-O, Ir-Hf-O, Ir-V-O, Ir-V-O, Ir-Zr-O and Ir-O. A ferroelectric thin film is formed on the electrode wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.
摘要翻译: 目的:提供具有良好表面平滑度和均匀性的单个c轴铅锗氧化物(PGO)薄膜电极,以通过在均匀的单相c轴PGO薄膜上形成PGO薄膜来提高PGO薄膜的表面粗糙度 金属电极。 构成:制备底物。 电极沉积在基板上,其中电极由从由铱和铱复合材料组成的材料组中取得的材料形成,其中铱复合材料取自IrO2,Ir-Ta-O, Ir-Ti-O,Ir-Nb-O,Ir-Al-O,Ir-Hf-O,Ir-VO,Ir-VO,Ir-Zr-O和Ir-O。 在电极上形成铁电薄膜,其中铁电薄膜表现出平滑度和均匀的厚度。
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公开(公告)号:KR1020020066997A
公开(公告)日:2002-08-21
申请号:KR1020020007479
申请日:2002-02-08
申请人: 샤프 가부시키가이샤
IPC分类号: H01L27/105
CPC分类号: H01L29/6684 , H01L21/28291 , H01L29/78391
摘要: PURPOSE: A method for fabricating a metal-ferro-metal oxide semiconductor(MFMOS)/metal-ferro-metal semiconductor(MFMS) non-volatile memory transistors is provided to prevent a ferroelectric material from being damaged in a plasma etching process by obviating the necessity of a gate stack etching process and minimizing etch-inducing damage. CONSTITUTION: A bottom electrode(16) is formed. A ferroelectric layer(24) is deposited over an active region beyond the margins of the bottom electrode. A top electrode(26) is deposited on the ferroelectric layer. A structure obtained by the above-described steps is metalized to form a source electrode(32), a gate electrode(34) and a drain electrode(36).
摘要翻译: 目的:提供一种用于制造金属 - 铁金属氧化物半导体(MFMOS)/金属 - 铁金属半导体(MFMS)非易失性存储晶体管的方法,以防止在等离子体蚀刻工艺中铁电材料被损坏, 栅极堆叠蚀刻工艺的必要性和最小化蚀刻诱导损伤。 构成:形成底部电极(16)。 在超过底部电极的边缘的有源区域上沉积铁电层(24)。 顶层电极(26)沉积在铁电层上。 通过上述步骤获得的结构被金属化以形成源电极(32),栅电极(34)和漏电极(36)。
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10.
公开(公告)号:KR1020020018056A
公开(公告)日:2002-03-07
申请号:KR1020010052045
申请日:2001-08-28
申请人: 샤프 가부시키가이샤
发明人: 슈솅텡 , 트위트더글라스제임스 , 울리치브루스데일 , 잉홍
IPC分类号: H01L27/10
CPC分类号: H01L21/84 , H01L27/1203 , H01L29/7378
摘要: PURPOSE: A high performance SiGe hetero-junction bipolar transistor BiCMOS on a silicon wafer on an insulator for achieving the performance of SiGe HBT is provided. CONSTITUTION: A semiconductor structure is provided with an SOI wafer, the CMOS formed on the wafer and the SiGe HBT formed on the wafer. In the method for producing the semiconductor structure, this method includes a process for controlling the SOI wafer having a plurality of active areas thereon, a process for forming the CMOS in the first active area on the wafer, and a process for forming the SiGe HBT in the other active area on the wafer.
摘要翻译: 目的:提供一种用于实现SiGe HBT性能的绝缘体硅晶片上的高性能SiGe异质结双极晶体管BiCMOS。 构成:半导体结构设置有SOI晶片,形成在晶片上的CMOS和形成在晶片上的SiGe HBT。 在制造半导体结构的方法中,该方法包括用于控制其上具有多个有源区的SOI晶片的工艺,在晶片的第一有源区中形成CMOS的工艺以及用于形成SiGe HBT的工艺 在晶片上的另一个有效区域。
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