-
公开(公告)号：US20150003506A1
公开(公告)日：2015-01-01
申请号：US13931721
申请日：2013-06-28
IPC分类号： H04B3/46
CPC分类号： H04B3/46 , H04L43/0823
摘要： Techniques for determining the spectral content of a data bus are described herein. An example of a device in accordance with the present techniques includes a data bus comprising a plurality of signal lines, a first phasor generator, and a second phasor generator. The first phasor generator obtains a first pulse sample based on the data to be transmitted over the data bus and generates a first phasor. The second phasor generator to obtain a second pulse sample based on the data to be transmitted over the data bus and generates a second phasor. The sum of the first phasor and the second phasor indicate, at least in part, the spectral content of the data to be transmitted over the data bus.
摘要翻译： 本文描述了用于确定数据总线的频谱内容的技术。 根据本技术的装置的示例包括包括多条信号线的数据总线，第一相量发生器和第二相量发生器。 第一相量发生器基于要通过数据总线发送的数据获得第一脉冲采样并产生第一相量。 第二相量发生器，用于基于要通过数据总线发送的数据获得第二脉冲采样并产生第二相量。 第一相量和第二相量的总和至少部分地表示要通过数据总线发送的数据的频谱内容。
-
2.发明申请Method, system, and apparatus high speed interconnect to improve data rates of memory subsystems 审中-公开方法，系统和设备高速互连，以提高存储器子系统的数据速率公开(公告)号：US20060198175A1
公开(公告)日：2006-09-07
申请号：US11072953
申请日：2005-03-03
申请人： Ashraf Badawi , Hany Fahmy , Adam Norman
发明人： Ashraf Badawi , Hany Fahmy , Adam Norman
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , H05K1/0237 , H05K1/181 , H05K3/0005
摘要： A technique is discussed for a different memory sub system topology to allow for separating impedance discontinuity The trace lengths from the MCH and the trace lengths to each memory device is calculated based at least in part on a frequency domain and time domain analysis. The new topology improves the impedance discontinuity that was evident in the P22P topology.
摘要翻译： 对于不同的存储器子系统拓扑来讨论允许分离阻抗不连续性的技术。至少部分地基于频域和时域分析来计算从MCH到每个存储器件的迹线长度的迹线长度。 新拓扑改善了P22P拓扑中显而易见的阻抗不连续性。
-
搜索结果
2 条记录 (耗时 0.011 秒)
